coreboot-gerrit June 2021

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Rizwan Qureshi (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55225/comment/4d3c97c7_4ba2db52 PS1, Line 95: memory fill_mrc_memory_init_params()? -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Stefan Reinauer, Julius Werner, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 4: (1 comment) File Documentation/technotes/2021-05-selectable-serial-console.md: https://review.coreboot.org/c/coreboot/+/54385/comment/6435f679_886fd2ea PS4, Line 127: To avoid adding complexity in the bootblock, bootblock is exempt from : this: When enabling this mode, bootblock stage code will not send data : to serial for performance reason > Just to ensure I understand this correctly: […] Yes. Do you think I should state this clearer in the doc? -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:14:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... soc/intel/alderlake/romstage: Refactor soc_memory_init_params function This patch create separate helper functions to fill-in required FSP-M UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly. TEST=FSP-M UPD dump shows no change without and with this code change. Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 174 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/55225/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036..8d39c74 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -60,13 +60,11 @@ } } -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, +static void fill_igd_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - const struct device *dev; - unsigned int i; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) m_cfg->InternalGfx = 1; else @@ -75,30 +73,6 @@ /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->RMT = config->RMT; - - /* CpuRatio Settings */ - if (config->cpu_ratio_override) - m_cfg->CpuRatio = config->cpu_ratio_override; - else - /* Set CpuRatio to match existing MSR value */ - m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; - - m_cfg->PrmrrSize = get_valid_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable BIOS Guard */ - m_cfg->BiosGuard = 0; - - /* UART Debug Log */ - m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; - if (CONFIG(DRIVERS_UART_8250IO)) - m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; - m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; - /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; @@ -116,27 +90,88 @@ m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; +} - /* Image clock: disable all clocks for bypassing FSP pin mux */ - memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); - - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; - /* Disable Lock PCU Thermal Management registers */ - m_cfg->LockPTMregs = 0; +static void fill_memory_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ m_cfg->ChHashMask = 0x30CC; +} + +static void fill_cpu_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + m_cfg->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + m_cfg->PrmrrSize = get_valid_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; +} + +static void fill_security_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + m_cfg->TmeEnable = CONFIG(INTEL_TME); +} + +static void fill_uart_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +} + +static void fill_ipu_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); +} + +static void fill_smbus_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); /* Enable SMBus controller */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); m_cfg->SmbusEnable = is_dev_enabled(dev); - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; +} +static void fill_misc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; +} + +static void fill_audio_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_HDA); m_cfg->PchHdaEnable = is_dev_enabled(dev); - m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to * configure GPIO pads for audio. Mainboard is expected to perform all GPIO @@ -147,11 +182,13 @@ memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; +} - /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ +static void disable_pcie_clksrc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + unsigned int i; + for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; @@ -161,20 +198,47 @@ m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; } +} - /* PCIE ports */ +static void fill_pch_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, CONFIG_MAX_PCH_ROOT_PORTS); +} - /* CPU PCIE ports */ +static void fill_cpu_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_CPU_ROOT_PORTS); +} - /* ISH */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); +static void fill_pcie_rp_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + disable_pcie_clksrc_memory_init_params(m_cfg, config); + + /* Configure PCH PCIE ports */ + fill_pch_pcie_memory_init_params(m_cfg, config); + + /* Configure CPU PCIE ports */ + fill_cpu_pcie_memory_init_params(m_cfg, config); +} + +static void fill_ish_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + /* Enable ISH controller */ m_cfg->PchIshEnable = is_dev_enabled(dev); +} + +static void fill_tcss_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev; /* Tcss USB */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI); @@ -189,8 +253,12 @@ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); m_cfg->TcssDma1En = is_dev_enabled(dev); +} - /* USB4/TBT */ +static void fill_usb4_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev; + dev = pcidev_path_on_root(SA_DEVFN_TBT0); m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); @@ -202,8 +270,10 @@ dev = pcidev_path_on_root(SA_DEVFN_TBT3); m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); +} - /* VT-d config */ +static void fill_vtd_memory_init_params(FSP_M_CONFIG *m_cfg) +{ m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; @@ -230,13 +300,12 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - /* Skip CPU replacement check */ - m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; +} - m_cfg->TmeEnable = CONFIG(INTEL_TME); - - /* Skip GPIO configuration from FSP */ - m_cfg->GpioOverride = 0x1; +static void fill_trace_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; /* CrashLog config */ if (CONFIG(SOC_INTEL_CRASHLOG)) { @@ -245,6 +314,55 @@ } } +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Fill IGD related FSP-M UPDs */ + fill_igd_memory_init_params(m_cfg, config); + + /* Fill Memory related FSP-M UPDs */ + fill_memory_memory_init_params(m_cfg, config); + + /* Fill CPU related FSP-M UPDs */ + fill_cpu_memory_init_params(m_cfg, config); + + /* Fill security related FSP-M UPDs */ + fill_security_memory_init_params(m_cfg); + + /* Fill UART debug related FSP-M UPDs */ + fill_uart_memory_init_params(m_cfg); + + /* Fill IPU related FSP-M UPDs */ + fill_ipu_memory_init_params(m_cfg); + + /* Fill SMBUS related FSP-M UPDs */ + fill_smbus_memory_init_params(m_cfg); + + /* Fill Miscellaneous FSP-M UPDs */ + fill_misc_memory_init_params(m_cfg, config); + + /* Fill Audio related FSP-M UPDs */ + fill_audio_memory_init_params(m_cfg, config); + + /* Fill PCIE related RP FSP-M UPDs */ + fill_pcie_rp_memory_init_params(m_cfg, config); + + /* Fill ISH related FSP-M UPD */ + fill_ish_memory_init_params(m_cfg); + + /* Fill TCSS related FSP-M UPD */ + fill_tcss_memory_init_params(m_cfg); + + /* Fill USB4/TBT related FSP-M UPD */ + fill_usb4_memory_init_params(m_cfg); + + /* Fill VT-d related FSP-M UPD */ + fill_vtd_memory_init_params(m_cfg); + + /* Fill trace related FSP-M UPD */ + fill_trace_memory_init_params(m_cfg); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_alderlake_config *config; -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/55224/comment/21a41625_87fe764f PS1, Line 180: DERIVE_SERIALIO_CFG_FROM_DEV_STATE Is this Kconfig required? The change looks like the direction we would want to go in for all mainboards i.e. eliminate the devicetree config and instead rely on SoC determining the correct values for the UPDs based on device state in devicetree and other configs. -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:05:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Paul Menzel, Stefan Reinauer, Julius Werner, Arthur Heymans. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File Documentation/technotes/2021-05-selectable-serial-console.md: https://review.coreboot.org/c/coreboot/+/54385/comment/62866c1b_6a7867e3 PS4, Line 127: To avoid adding complexity in the bootblock, bootblock is exempt from : this: When enabling this mode, bootblock stage code will not send data : to serial for performance reason Just to ensure I understand this correctly: 1. bootblock will default to console enabled if it's compiled in. 2. If Kconfig to disable the default is set, bootblock will default to console disabled without looking at the CBFS file. All other stages differ from bootblock i.e. they check for the flag in CBFS file if Kconfig is set. Is that correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Jun 2021 12:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... soc/intel/skylake: Auto-configure SerialIoDevMode UPD Introduce the `DERIVE_SERIALIO_CFG_FROM_DEV_STATE` Kconfig symbol, which allows omitting the `SerialIoDevMode` setting from devicetrees where the SerialIO settings can be derived from the PCI devices' state. Also, when the `INTEL_LPSS_UART_FOR_CONSOLE` option is selected, configure the UART specified by `UART_FOR_CONSOLE` to have FSP skip initialisation for it. Also, as an example, transform hp/280_g2 to make use of this code. Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/Kconfig M src/mainboard/hp/280_g2/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c 4 files changed, 51 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/55224/1 diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index 10f6828..4f18548 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 98fccc9..aefebf1 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -5,10 +5,6 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" - register "SerialIoDevMode" = "{ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ - }" - register "eist_enable" = "1" device cpu_cluster 0 on @@ -76,7 +72,7 @@ }" # DevSlp not supported end - device pci 19.0 on end # UART #2 + device pci 19.0 on end # UART #2 (routed to debug header) device pci 1c.0 off end # RP #1 device pci 1c.1 off end # RP #2 device pci 1c.2 off end # RP #3 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3f02974..1fbdc39 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -177,6 +177,14 @@ string default "8086,0406" +config DERIVE_SERIALIO_CFG_FROM_DEV_STATE + bool + help + Selected by mainboards where the values for the `SerialIoDevMode` FSP + UPD can be derived from the PCI devices' state in the devicetree, and + the INTEL_LPSS_UART_FOR_CONSOLE and UART_FOR_CONSOLE Kconfig settings. + When enabled, the `SerialIoDevMode` setting in chip config is useless. + config SKYLAKE_SOC_PCH_H bool default n diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d4e8341..48b9c0b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <bootsplash.h> #include <cbmem.h> #include <fsp/api.h> @@ -220,6 +221,40 @@ .init = &soc_init_pre_device, }; +static void fsp_serialio_config(FSP_S_CONFIG *params, struct soc_intel_skylake_config *config) +{ + const unsigned int serialio_devfn[] = { + [PchSerialIoIndexI2C0] = PCH_DEVFN_I2C0, + [PchSerialIoIndexI2C1] = PCH_DEVFN_I2C1, + [PchSerialIoIndexI2C2] = PCH_DEVFN_I2C2, + [PchSerialIoIndexI2C3] = PCH_DEVFN_I2C3, + [PchSerialIoIndexI2C4] = PCH_DEVFN_I2C4, + [PchSerialIoIndexI2C5] = PCH_DEVFN_I2C5, + [PchSerialIoIndexSpi0] = PCH_DEVFN_GSPI0, + [PchSerialIoIndexSpi1] = PCH_DEVFN_GSPI1, + [PchSerialIoIndexUart0] = PCH_DEVFN_UART0, + [PchSerialIoIndexUart1] = PCH_DEVFN_UART1, + [PchSerialIoIndexUart2] = PCH_DEVFN_UART2, + }; + _Static_assert(ARRAY_SIZE(serialio_devfn) == PchSerialIoIndexMax, + "serialio_devfn array size is wrong"); + + _Static_assert(!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) || + (CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 2), + "Value for UART_FOR_CONSOLE is invalid"); + + for (size_t i = 0; i < ARRAY_SIZE(serialio_devfn); i++) { + const bool pcidev_on = is_dev_enabled(pcidev_path_on_root(serialio_devfn[i])); + params->SerialIoDevMode[i] = pcidev_on ? PchSerialIoPci : PchSerialIoDisabled; + } + + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) { + const size_t i = PchSerialIoIndexUart0 + CONFIG_UART_FOR_CONSOLE; + if (params->SerialIoDevMode[i] != PchSerialIoDisabled) + params->SerialIoDevMode[i] = PchSerialIoSkipInit; + } +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -347,8 +382,12 @@ params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); - memcpy(params->SerialIoDevMode, config->SerialIoDevMode, - sizeof(params->SerialIoDevMode)); + if (CONFIG(DERIVE_SERIALIO_CFG_FROM_DEV_STATE)) { + fsp_serialio_config(params, config); + } else { + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + } dev = pcidev_path_on_root(PCH_DEVFN_CIO); params->PchCio2Enable = dev && dev->enabled; -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc: common: gpio: Add support for common GPIO driver
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55076 ) Change subject: soc: common: gpio: Add support for common GPIO driver ...................................................................... soc: common: gpio: Add support for common GPIO driver Add common gpio functionalities across qualcomm soc targets. This common gpio driver would allow the consumers to be able to configure gpio function, set/get gpio direction as input/output, configure the gpio as pull-up/pull-down, configure the gpio as an IRQ and also query the gpio irq status. The GPIO pin definition would be SoC specific. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55076 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/qualcomm/common/gpio.c A src/soc/qualcomm/common/include/soc/gpio_common.h 2 files changed, 189 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/gpio.c b/src/soc/qualcomm/common/gpio.c new file mode 100644 index 0000000..1ed8e8a --- /dev/null +++ b/src/soc/qualcomm/common/gpio.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + uint32_t reg_val; + + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & GPIO_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_INPUT); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_INPUT); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_INPUT); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_INPUT); + + clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHFT, type << GPIO_INTR_DECT_CTL_SHFT); + clrsetbits32(&regs->intr_cfg, GPIO_INTR_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHFT, GPIO_INTR_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return GPIO_INTR_STATUS_DISABLE; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + + return GPIO_INTR_STATUS_ENABLE; +} diff --git a/src/soc/qualcomm/common/include/soc/gpio_common.h b/src/soc/qualcomm/common/include/soc/gpio_common.h new file mode 100644 index 0000000..0ad582d --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/gpio_common.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_COMMON_GPIO_H_ +#define _SOC_QUALCOMM_COMMON_GPIO_H_ + +#include <soc/gpio.h> +#include <soc/addressmap.h> + +#define GPIO_FUNC_GPIO 0 + +/* GPIO TLMM INTR: Mask */ +enum gpio_tlmm_intr_bmsk { + GPIO_INTR_STATUS_MASK = 0x1, + GPIO_INTR_DECT_CTL_MASK = 0x3, +}; + +/* GPIO TLMM: Mask */ +enum gpio_tlmm_bmsk { + GPIO_BMSK = 0x1, + GPIO_CFG_PULL_BMSK = 0x3, + GPIO_CFG_FUNC_BMSK = 0xF, + GPIO_CFG_DRV_BMSK = 0x7, +}; + +/* GPIO TLMM INTR: Shift */ +enum gpio_tlmm_intr_shft { + GPIO_INTR_DECT_CTL_SHFT = 2, + GPIO_INTR_RAW_STATUS_EN_SHFT = 4, +}; + +/* GPIO TLMM: Shift */ +enum gpio_tlmm_shft { + GPIO_CFG_PULL_SHFT = 0, + GPIO_CFG_FUNC_SHFT = 2, + GPIO_CFG_DRV_SHFT = 6, + GPIO_CFG_OE_SHFT = 9, +}; + +/* GPIO IO: Shift */ +enum gpio_io_shft { + GPIO_IO_IN_SHFT, + GPIO_IO_OUT_SHFT, +}; + +/* GPIO INTR STATUS */ +enum gpio_irq_status { + GPIO_INTR_STATUS_DISABLE, + GPIO_INTR_STATUS_ENABLE, +}; + +/* GPIO TLMM: Direction */ +enum gpio_direction { + GPIO_INPUT, + GPIO_OUTPUT, +}; + +/* GPIO TLMM: Pullup/Pulldown */ +enum gpio_pull { + GPIO_NO_PULL, + GPIO_PULL_DOWN, + GPIO_KEEPER, + GPIO_PULL_UP, +}; + +/* GPIO TLMM: Drive Strength */ +enum gpio_drv_str { + GPIO_2MA, + GPIO_4MA, + GPIO_6MA, + GPIO_8MA, + GPIO_10MA, + GPIO_12MA, + GPIO_14MA, + GPIO_16MA, +}; + +enum gpio_irq_type { + IRQ_TYPE_LEVEL, + IRQ_TYPE_RISING_EDGE, + IRQ_TYPE_FALLING_EDGE, + IRQ_TYPE_DUAL_EDGE, +}; + +typedef struct { + u32 addr; +} gpio_t; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_COMMON_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 Gerrit-Change-Number: 55076 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram regions index order corrected
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55102 ) Change subject: sc7280: Reserve wlan & wpss dram regions index order corrected ...................................................................... sc7280: Reserve wlan & wpss dram regions index order corrected BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55102 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/sc7280/soc.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 19cfbd9..c0fa32f 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -12,9 +12,9 @@ ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); - reserved_ram_resource(dev, 4, (uintptr_t)_dram_wlan / KiB, + reserved_ram_resource(dev, 2, (uintptr_t)_dram_wlan / KiB, REGION_SIZE(dram_wlan) / KiB); - reserved_ram_resource(dev, 5, (uintptr_t)_dram_wpss / KiB, + reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB, REGION_SIZE(dram_wpss) / KiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Gerrit-Change-Number: 55102 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_apl2: Disable unused I2C controllers
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55090 ) Change subject: mb/siemens/mc_apl2: Disable unused I2C controllers ...................................................................... mb/siemens/mc_apl2: Disable unused I2C controllers Only I2C controller 3 is used on this mainboard. Disable all other controllers. Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 06f4c05..1749636 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -97,9 +97,9 @@ end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 on end # - I2C 0 - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 + device pci 16.0 off end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 device pci 16.3 on # - I2C 3 # Enable external RTC chip chip drivers/i2c/rx6110sa @@ -115,10 +115,10 @@ device i2c 0x32 on end # RTC RX6110 SA end end - device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Gerrit-Change-Number: 55090 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55160 ) Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... Patch Set 5: (4 comments) File util/amdfwtool/replace.sh: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120761): https://review.coreboot.org/c/coreboot/+/55160/comment/f21e5ff4_093d8a3e PS5, Line 12: CBFS_ADDRESS=$(eval $CBFSTOOL $IMAGE layout | grep "^'COREBOOT'" | sed "s/'COREBOOT' (CBFS, size [0-9]\+, offset $[0-9]\+$)/\1/g") line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120761): https://review.coreboot.org/c/coreboot/+/55160/comment/285ff9e8_71f44e6d PS5, Line 15: AMDFW_ADDRESS=0x$(eval printf %x $(eval expr 4294967295 + 1 - $(($ROMSIZE)) + $CBFS_ADDRESS + $AMDFW_OFFSET + 64)) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120761): https://review.coreboot.org/c/coreboot/+/55160/comment/92ffe7e8_f32c572c PS5, Line 72: --instance 0 --apcb BiosDirL20_Typex60.bin --instance 10 --apcb BiosDirL20_Typex68.bin --apob-base 0x2001000 --bios-bin $BIOS_BIN_FILE --bios-bin-dest $BIOS_BIN_DEST --bios-uncomp-size $BIOS_BIN_SIZE --soft-fuse $SOFT_FUSE --use-pspsecureos --load-s0i3 --combo-capable "--token-unlock" --spi-read-mode 2 --spi-speed 0 --spi-micron-flag 0 --config "fw.cfg" --soc-name "Cezanne" --flashsize $ROMSIZE \ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120761): https://review.coreboot.org/c/coreboot/+/55160/comment/ed10c18b_3da11387 PS5, Line 84: $CBFSTOOL $IMAGE_NEW add -f amdfw_n.rom -n apu/amdfw -t raw -r COREBOOT -b $(($AMDFW_ADDRESS)) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 04 Jun 2021 12:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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