Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55228 )
Change subject: 3rdparty/fsp: Update submodule pointer to newest master
......................................................................
3rdparty/fsp: Update submodule pointer to newest master
Newest master include this changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for IOTG Tiger Lake SKUs
3. Update the FSP package to latest version for Apollo Lake,
Comet Lake and Tiger Lake (client SKUs)
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
---
M 3rdparty/fsp
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/55228/1
diff --git a/3rdparty/fsp b/3rdparty/fsp
index e7138bf..7954a8d 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit e7138bf11508b8b82350bd17fb611b67c0c64e6b
+Subproject commit 7954a8db808942a7430a00f4e5a757eb84951edc
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 )
Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Well, it doesn't account for devices in ACPI mode. […]
I'll know better once I've updated all boards 😜
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 )
Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> You mentioned in IRC that this does not handle all (corner) cases. […]
Well, it doesn't account for devices in ACPI mode. However, I don't think any board uses SerialIO devices in ACPI mode.
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Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
You mentioned in IRC that this does not handle all (corner) cases. Maybe add some words on this to the commit msg?
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Change subject: mb/google/dedede/var/kracko: Add P-sensor support
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn
......................................................................
Patch Set 6:
(6 comments)
File src/soc/intel/alderlake/chip.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/48947437_b9dc110a
PS6, Line 44: * Specifies which Type-C Ports are enabled on the system
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/4b78cc11_3940d89f
PS6, Line 45: * each bit represents a port starting at 0
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/8d87d99f_8e315403
PS6, Line 46: * Example: set value to 0x3 for ports 0 and 1 to be enabled
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/1643e21b_986b0711
PS6, Line 47: */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/333dd71e_6fdfc732
PS6, Line 48: uint8_t UsbTcPortEn;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120774):
https://review.coreboot.org/c/coreboot/+/54334/comment/2ee34b88_edfe7aa8
PS6, Line 48: uint8_t UsbTcPortEn;
please, no spaces at the start of a line
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Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55225/comment/48f15146_d48539b5
PS1, Line 320: /* Fill IGD related FSP-M UPDs */
: fill_igd_memory_init_params(m_cfg, config);
:
: /* Fill Memory related FSP-M UPDs */
: fill_memory_memory_init_params(m_cfg, config);
:
: /* Fill CPU related FSP-M UPDs */
: fill_cpu_memory_init_params(m_cfg, config);
:
: /* Fill security related FSP-M UPDs */
: fill_security_memory_init_params(m_cfg);
:
: /* Fill UART debug related FSP-M UPDs */
: fill_uart_memory_init_params(m_cfg);
:
: /* Fill IPU related FSP-M UPDs */
: fill_ipu_memory_init_params(m_cfg);
:
: /* Fill SMBUS related FSP-M UPDs */
: fill_smbus_memory_init_params(m_cfg);
:
: /* Fill Miscellaneous FSP-M UPDs */
: fill_misc_memory_init_params(m_cfg, config);
:
: /* Fill Audio related FSP-M UPDs */
: fill_audio_memory_init_params(m_cfg, config);
:
: /* Fill PCIE related RP FSP-M UPDs */
: fill_pcie_rp_memory_init_params(m_cfg, config);
:
: /* Fill ISH related FSP-M UPD */
: fill_ish_memory_init_params(m_cfg);
:
: /* Fill TCSS related FSP-M UPD */
: fill_tcss_memory_init_params(m_cfg);
:
: /* Fill USB4/TBT related FSP-M UPD */
: fill_usb4_memory_init_params(m_cfg);
:
: /* Fill VT-d related FSP-M UPD */
: fill_vtd_memory_init_params(m_cfg);
:
: /* Fill trace related FSP-M UPD */
: fill_trace_memory_init_params(m_cfg);
> I don't think we need a comment on every function call. […]
Thanks Angel for awesome feedback, i will adhere to this and it make sense to me as well
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