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Change subject: drivers/generic/ioapic: Use arch/x86/ioapic
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55225/comment/ae30b6d9_1d7415b0
PS1, Line 12: This would help to increase the code readability and in future
: meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly
> I like this change! :).
Me too!
I have been secretly hoping, and maybe I should ask instead, is if we could get the UPDs separated by functional area or IP block, etc. kind of like how it's organized in this change, e.g.:
```
struct FSPM_UPD {
struct CPU_UPD {
uintptr_t tseg_base;
size_t tseg_size;
};
struct SERIALIO_UPD {
struct i2c_upd i2c[NUM_I2C];
struct gspi_upd ....;
};
...
};
```
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55225/comment/8bbe216a_6641e73c
PS1, Line 95: memory
> I would drop the `memory_init_params` part because FSP-M is not just about memory init (although the […]
+1 to `fill_fspm_*_params`
https://review.coreboot.org/c/coreboot/+/55225/comment/4ec0ddee_e0f7887a
PS1, Line 244: dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI);
: m_cfg->TcssXhciEn = is_dev_enabled(dev);
:
: dev = pcidev_path_on_root(SA_DEVFN_TCSS_XDCI);
: m_cfg->TcssXdciEn = is_dev_enabled(dev);
:
: /* TCSS DMA */
: dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
: m_cfg->TcssDma0En = is_dev_enabled(dev);
:
: dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
: m_cfg->TcssDma1En = is_dev_enabled(dev);
Just thinking out loud, maybe we want (another change) to add a is_devfn_enabled?
```
bool is_devfn_enabled(unsigned int devfn)
{
const struct device *dev = pcidev_path_on_root(devfn);
return is_dev_enabled(dev);
}
```
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Change subject: arch/x86/ioapic: Split some ioapic utility functions
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/common: Fix X2APIC NMI entry in ACPI MADT
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Patch Set 1: Code-Review+2
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Change subject: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE
......................................................................
Patch Set 2:
(1 comment)
File src/include/cpu/x86/lapic.h:
https://review.coreboot.org/c/coreboot/+/55073/comment/8988a5b1_0f3d70a1
PS2, Line 78: msr.lo |= LAPIC_BASE_MSR_X2APIC_MODE;
This is not always a valid change of mode. If the LAPIC_BASE_MSR_ENABLE bit is not set, this is invalid.
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Change subject: sb/intel/lynxpoint: Drop P_LVLx support in FADT
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Patch Set 1: Code-Review+2
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