coreboot-gerrit June 2021

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Change in coreboot[master]: FSP2.0 platforms: Use bootloader reserved memory for BERT
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Arthur Heymans, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55142 to look at the new patch set (#3). Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT ...................................................................... FSP2.0 platforms: Use bootloader reserved memory for BERT Currently, a cbmem entry is used to store the BERT data, but when ACPI_BERT is defined, the FSP will save some memory in its reserved area above TOLUM to store the ACPI BERT. This patch moves the area BERT data is stored from cbmem to this reserved region. TEST=1) Trigger an event which will create a BERT 2) Verify BERT contents look valid 3) Ensure reserved region is covered by an e820 entry marked RESERVED 4) Ensure cbmem contents are still valid Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/systemagent/memmap.c 2 files changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55142/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 Gerrit-Change-Number: 55142 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Werner Zeh, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55012 ) Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/i82371eb/fadt.c: https://review.coreboot.org/c/coreboot/+/55012/comment/311022dc_3040d9b5 PS2, Line 45: /* not supported */ The PIIX4 datasheet doesn't mention anything about centuries nor centenary (I looked for "cent"). I'm not sure if it's the same thing, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:30:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage: unbreak BERT support
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Raul Rangel, Francois Toguo Fotso, Marshall Dawson, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54738 ) Change subject: arch/x86/acpi_bert_storage: unbreak BERT support ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2a115f3f2879c3d3a02f3ee8aee82f00f2ac7 Gerrit-Change-Number: 54738 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Update CrashLog data length tracking
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Francois Toguo Fotso, Martin Roth, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55006 ) Change subject: soc/intel/common: Update CrashLog data length tracking ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97ff14d62bda69389c7647fcbbf23d5cab2b36e6 Gerrit-Change-Number: 55006 Gerrit-PatchSet: 3 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:25:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: rework BERT SSDT generation logic
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Francois Toguo Fotso, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55054 ) Change subject: acpi: rework BERT SSDT generation logic ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea Gerrit-Change-Number: 55054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:25:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: rework BERT SSDT generation logic
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Francois Toguo Fotso, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55054 ) Change subject: acpi: rework BERT SSDT generation logic ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea Gerrit-Change-Number: 55054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:24:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55015 ) Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55015/comment/d8fc7d02_b6f9c106 PS3, Line 232: 0x1 > nit: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Gerrit-Change-Number: 55015 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:24:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... src/mainboard: Add Star Labs labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Documentation/distributions.md M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop.md M MAINTAINERS A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 46 files changed, 2,163 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 5740527..587603a 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -29,6 +29,13 @@ third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io). +### Star Labs + +[Star Labs](https://starlabs.systems/) offer a range of laptops designed and +built specifically for Linux. All are now available with coreboot firmware, +using Tianocore as the payload, and which include an NVRAM option to disable +the Intel Management Engine. + ### System76 [System76](https://system76.com/) manufactures Linux laptops, desktops, and diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a08cc43..0900bf6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -169,6 +169,10 @@ - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) +## Star Labs Systems + +- [Labtop Mk IV / StarBook Mk V](starlabs/labtop.md) + ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) diff --git a/Documentation/mainboard/starlabs/labtop.md b/Documentation/mainboard/starlabs/labtop.md new file mode 100644 index 0000000..cc91dd5 --- /dev/null +++ b/Documentation/mainboard/starlabs/labtop.md @@ -0,0 +1,174 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-10710U (Comet Lake) + - Intel i3-10110U (Comet Lake) + - Intel i7-8550u (Kaby Lake Refresh) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 620 + - GOP driver is recommended, VBT is provided + - eDP 13-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 16GB on-board for Comet Lake platforms[^1] + - 8GB on-board for Kaby Lake Refresh platform. +- Networking + - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) + - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - USB 3.1 Gen 2 Type-C (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: + +Comet Lake and Kaby Lake configurations: +- Intel Flash Descriptor file (descriptor.bin) +- Intel Management Engine firmware (me.bin) + +Comet Lake configuration only: +- ITE IT8987E firmware (it8987-x.xx.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +##### LabTop Mk IV (Comet Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml +make +``` + +##### LabTop Mk III (Kaby Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* Only available on Star Labtop Mk IV and Star LabTop Mk III +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. +![fwupd version](https://cdn.shopify.com/s/files/1/2059/5897/files/fwupdV.png?v=161… +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings. +2\. When the BIOS settings load, use the arrow keys to navigate to the advanced tab\. Here you will see BIOS Lock\. +3\. Press `Enter` to change this setting from **Enabled** to **Disabled** + +![Disable BIOS Lock](https://cdn.shopify.com/s/files/1/2059/5897/files/IMG_20210120_094049… + +4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: +![Switch Branch](https://cdn.shopify.com/s/files/1/2059/5897/files/SwitchBranch.png?… +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + +![Installed coreboot](https://cdn.shopify.com/s/files/1/2059/5897/files/Complete.png?v=… +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. \ No newline at end of file diff --git a/MAINTAINERS b/MAINTAINERS index 74f1854..b2fbaca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -446,6 +446,13 @@ +STAR LABS MAINBOARDS +M: Sean Rhodes <sean(a)starlabs.systems> +S: Maintained +F: src/mainboard/starlabs/ + + + SYSTEM76 MAINBOARDS M: Jeremy Soller <jeremy(a)system76.com> S: Maintained @@ -517,6 +524,11 @@ S: Maintained F: src/ec/lenovo/ +STARLABS EC +M: Sean Rhodes <sean(a)starlabs.systems> +S: Maintained +F: src/ec/starlabs/ + SYSTEM76 EC M: Jeremy Soller <jeremy(a)system76.com> S: Maintained diff --git a/src/mainboard/starlabs/Kconfig b/src/mainboard/starlabs/Kconfig new file mode 100644 index 0000000..4df0588 --- /dev/null +++ b/src/mainboard/starlabs/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_STARLABS + +choice + prompt "Mainboard model" + +source "src/mainboard/starlabs/*/Kconfig.name" + +endchoice + +source "src/mainboard/starlabs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Star Labs" + +endif # VENDOR_STARLABS diff --git a/src/mainboard/starlabs/Kconfig.name b/src/mainboard/starlabs/Kconfig.name new file mode 100644 index 0000000..7aab0da --- /dev/null +++ b/src/mainboard/starlabs/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_STARLABS + bool "Star Labs" diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig new file mode 100644 index 0000000..597ffd9 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -0,0 +1,122 @@ +if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_LABTOP_KBL + +# +# LabTop Mk IV CML Board uses the following devices: +# +# GigaDevice GD25Q64C (8192KB) SPI NOR flash (KBL) +# Winbond 25Q128JVSQ (16384KB) SPI NOR flash (CML) +# Infineon SLB9670VQ SPI TPM2.0 device +# Realtek ALC256 audio CODEC +# ITE IT8987 Embedded Controller +# Analogix ANX7447 crosspoint switch +# +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 if BOARD_STARLABS_LABTOP_CML + select BOARD_ROMSIZE_KB_8192 if BOARD_STARLABS_LABTOP_KBL + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB +# select HAVE_IFD_BIN +# select HAVE_ME_BIN + select MAINBOARD_HAS_LIBGFXINIT if BOARD_STARLABS_LABTOP_KBL + select EC_STARLABS_IT8987 if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_LABTOP_KBL + select EC_STARLABS_IT_BIN if BOARD_STARLABS_LABTOP_CML + select SYSTEM_TYPE_LAPTOP + select SPI_FLASH_WINBOND if BOARD_STARLABS_LABTOP_CML + select SPI_FLASH_GIGADEVICE if BOARD_STARLABS_LABTOP_KBL + select DISABLE_ACPI_HIBERNATE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config MAINBOARD_DIR + string + default "starlabs/labtop" + +config VARIANT_DIR + string + default "cml" if BOARD_STARLABS_LABTOP_CML + default "kbl" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_PART_NUMBER + string + default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML + default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_FAMILY + string + default "L4" if BOARD_STARLABS_LABTOP_CML + default "L3" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "LabTop" + +config MAX_CPUS + int + default 8 if BOARD_STARLABS_LABTOP_KBL + default 12 + +#config DRIVER_TPM_SPI_CHIP +# int +# default 2 + +config UART_FOR_CONSOLE + int + default 2 + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_0_flashdescriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_2_intel_me.bin" + +config ME_STATE_BY_CMOS + bool + default y + +config EC_STARLABS_IT_BIN + bool + default n + default y if BOARD_STARLABS_LABTOP_CML + +config EC_STARLABS_IT_BIN_PATH + string + depends on EC_STARLABS_IT_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_8_ec.bin" + +config VGA_BIOS_ID + string + default "8086,9b41" if BOARD_STARLABS_LABTOP_CML + default "8086,5917" if BOARD_STARLABS_LABTOP_KBL + +config TIANOCORE_BOOTSPLASH_FILE + string + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +endif diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name new file mode 100644 index 0000000..087f6d27 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -0,0 +1,9 @@ +comment "Star Labs LabTop Mk IV" + +config BOARD_STARLABS_LABTOP_CML + bool "Star Labs LabTop Mk IV (i3-10110u and i7-10710u)" + select SOC_INTEL_COMETLAKE_1 + +config BOARD_STARLABS_LABTOP_KBL + bool "Star Labs LabTop Mk IV (i7-8550u)" + select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc new file mode 100644 index 0000000..f89bda7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += ./spd +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += bootblock.c + +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/starlabs/labtop/acpi/ec.asl b/src/mainboard/starlabs/labtop/acpi/ec.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl new file mode 100644 index 0000000..2abd1a7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" + + /* Power button device. */ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (PBST, One) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } +} + +/* + * The Intel Comet Lake platform doesn't support SoundWire but there + * is a kernel bug in some 5.10.x releases. + * + * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More + * details can be found at https://bit.ly/3ttdffG but it appears to + * be triggered by missing SoundWire ACPI entries. + * + * Add the minimal set to make it work again. + */ +Scope (_SB.PCI0.HDAS) +{ + Device (SNDW) + { + Name (_ADR, 0x40000000) + + Name (_CID, Package (0x02) + { + "PRP00001", + "PNP0A05" + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0B) + } + } +} + +/* + * ITE IT8987E Embedded Controller + * + * We include this here as we need to support different levels within + * the ACPI DSDT tree structure. + */ + +#define EC_GPE_SWI 0x49 /* GPP_E15 */ +#define EC_GPE_SCI 0x50 /* GPP_E16 */ + +#include <ec/starlabs/it8987/acpi/ec.asl> diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl new file mode 100644 index 0000000..d8eb818 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.H_EC.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.H_EC.WAK (Arg0) +} diff --git a/src/mainboard/starlabs/labtop/acpi/superio.asl b/src/mainboard/starlabs/labtop/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/board_info.txt b/src/mainboard/starlabs/labtop/board_info.txt new file mode 100644 index 0000000..9543745 --- /dev/null +++ b/src/mainboard/starlabs/labtop/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: LabTop Mk IV +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/labtop/bootblock.c b/src/mainboard/starlabs/labtop/bootblock.c new file mode 100644 index 0000000..5d9cf02 --- /dev/null +++ b/src/mainboard/starlabs/labtop/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <console/console.h> +#include <bootblock_common.h> + +#include "baseboard/variants.h" +#include "variant/gpio.h" + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default new file mode 100644 index 0000000..12b2440 --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +hyper_threading=Enable +kbl_timeout=30 seconds +fn_ctrl_swap=Disable +me_state=Disable diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout new file mode 100644 index 0000000..3da79cc --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 5 hyper_threading +401 1 e 5 vtd +409 1 e 5 me_state + +# coreboot config options: EC +512 3 e 4 kbl_timeout +520 1 e 1 fn_ctrl_swap + +# coreboot config options: southbridge +536 2 e 6 power_on_after_fail + +#408 1 h 1 preserve_smmstore + +# coreboot config options: check sums +984 16 h 0 check_sum + +# embedded controller settings (outwith the checksummed area) +1000 1 h 0 fn_lock_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 30 seconds +4 1 1 minute +4 2 3 minutes +4 3 5 minutes +4 4 Never + +5 0 Enable +5 1 Disable + +6 0 Disable +6 1 Enable +6 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl new file mode 100644 index 0000000..f3492db --- /dev/null +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> +#if CONFIG(BOARD_STARLABS_LABTOP_CML) + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> +#else + #include <soc/intel/skylake/acpi/globalnvs.asl> +#endif + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { +#if CONFIG(BOARD_STARLABS_LABTOP_CML) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> +#else + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> +#endif + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/labtop/hda_verb.c b/src/mainboard/starlabs/labtop/hda_verb.c new file mode 100644 index 0000000..c260297 --- /dev/null +++ b/src/mainboard/starlabs/labtop/hda_verb.c @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c new file mode 100644 index 0000000..4fe4af3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> +#include <types.h> +#include <uuid.h> + +#include <ec/starlabs/it8987/ec.h> + +/* Override the BIOS version using smbios_mainboard_bios_version() */ +const char *smbios_mainboard_bios_version(void) +{ + return "6"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it8987_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +/* Override smbios_system_manufacturer */ +const char *smbios_system_manufacturer(void) +{ + return "Star Labs"; +} + +/* Override smbios_system_sku */ +const char *smbios_system_sku(void) +{ +#if CONFIG(BOARD_STARLABS_LABTOP_CML) + return "L4"; +#else + return "L3-U"; +#endif +} + +/* Override smbios_mainboard_features_flags */ +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAG_HOSTING_BOARD | SMBIOS_FEATURE_FLAG_REPLACEABLE; +} + +/* Override smbios_mainboard_location_in_chassis */ +const char *smbios_mainboard_location_in_chassis(void) +{ + return "Default"; +} + +/* Override smbios_mainboard_board_type */ +smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_MOTHERBOARD; +} + +/* Override smbios_mainboard_asset_tag */ +const char *smbios_mainboard_asset_tag(void) +{ + return "Default"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +/* Override smbios_chassis_version */ +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +/* Override smbios_chassis_serial_number */ +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +/* Override smbios_chassis_asset_tag */ +const char *smbios_chassis_asset_tag(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} diff --git a/src/mainboard/starlabs/labtop/ramstage.c b/src/mainboard/starlabs/labtop/ramstage.c new file mode 100644 index 0000000..5ba0778 --- /dev/null +++ b/src/mainboard/starlabs/labtop/ramstage.c @@ -0,0 +1,25 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/ramstage.h> +#include <option.h> +#include "variant/gpio.h" + +#if CONFIG(BOARD_STARLABS_LABTOP_CML) +void mainboard_silicon_init_params(FSPS_UPD * supd) +#else +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +#endif +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc new file mode 100644 index 0000000..9e7f4e3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Schematics for this platform show Samsung K4A8G165WB-BCRC devices +# which are 8Gb, 2400Mbps 512Mx16 devices. +# +# The hardware platforms used for testing are fitted with a Micron part +# which has the FBGA identifier "D9ZFW". The identification tool at +# https://www.micron.com/support/tools-and-utilities/fbga identifies +# this as the MT40A1G16KD-062E:E. These are 16Gb, 1Gx16 devices. +# +# We have defined both SPD options below. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron-MT40A1G16KD-062E-E # 0b0001 +SPD_SOURCES += empty_ddr4 # 0b0010 +SPD_SOURCES += empty_ddr4 # 0b0011 +SPD_SOURCES += empty_ddr4 # 0b0100 +SPD_SOURCES += empty_ddr4 # 0b0101 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0110 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000..1777847 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex new file mode 100644 index 0000000..36b85a2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex @@ -0,0 +1,33 @@ +# K4A8G165WB-BCRC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 0B E3 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 42 42 30 2D 43 52 43 20 20 20 20 00 80 CE +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/spd.h b/src/mainboard/starlabs/labtop/spd/spd.h new file mode 100644 index 0000000..6cd9416 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include <variant/gpio.h> + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/starlabs/labtop/spd/spd_util.c b/src/mainboard/starlabs/labtop/spd/spd_util.c new file mode 100644 index 0000000..7d23dfb --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd_util.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = {{0, 6, 3, 1, 5, 2, 7, 4}, {7, 5, 3, 6, 2, 4, 0, 1} }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h new file mode 100644 index 0000000..47e2688 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MEMORY_H +#define MEMORY_H + +u8 get_memory_config_straps(void); +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h new file mode 100644 index 0000000..cfcc6ab --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..454749f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include <soc/gpio.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc new file mode 100644 index 0000000..79b824b --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd new file mode 100644 index 0000000..9018104 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 16M { + BIOS@0x400000 0xC00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt new file mode 100644 index 0000000..bae9210 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb new file mode 100644 index 0000000..a6773f1 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -0,0 +1,186 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + /* Touchpad */ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 20, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# Graphics (soc/intel/cannonlake/graphics.c) + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "3" # 1s + register "PchPmSlpSusMinAssert" = "3" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + + # Enable eDP device + # register "DdiPortEdp" = "1" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal Device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # SD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CNVi Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC - not fitted + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (SSD x4) + device pci 00.0 on end + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 (LAN) + device pci 1d.5 off end # PCI Express Port 14 (WLAN) + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00fc0201" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x000c0081" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x119e + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h new file mode 100644 index 0000000..a20be31 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_GPIO_H_ +#define _VARIANT_GPIO_H_ + +#include "baseboard/variants.h" + +#ifndef __ACPI__ + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_E22, 1, PLTRST), + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_A7, 0x40100100, 0x3000), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A19, UP_20K), + PAD_NC(GPP_A20, UP_20K), + PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A22, UP_20K), + PAD_NC(GPP_A23, UP_20K), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000), + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPO(GPP_B22, 0, DEEP), + PAD_CFG_GPO(GPP_B23, 1, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C2, 1, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_C5, 0x40880100, 0x0000), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + _PAD_CFG_STRUCT(GPP_C8, 0x80100100, 0x3000), + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C11, 0x40100100, 0x0000), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_D10, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + PAD_CFG_GPO(GPP_D12, 0, DEEP), + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + PAD_CFG_GPO(GPP_D16, 0, PWROK), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), + PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_E3, 0x82040100, 0x0000), + _PAD_CFG_STRUCT(GPP_E4, 0x80880100, 0x3000), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI(GPP_E7, NONE, PLTRST), + PAD_NC(GPP_E8, NONE), + _PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000), + _PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x3000), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_F0, 0x00000301, 0x0000), + PAD_CFG_GPO(GPP_F1, 0, PWROK), + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_F3, 0x84000300, 0x3000), + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, DN_20K), + PAD_NC(GPP_H0, UP_20K), + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + PAD_NC(GPP_H3, UP_20K), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_NC(GPP_H16, NONE), + PAD_CFG_GPO(GPP_H17, 0, DEEP), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000), + PAD_CFG_GPO(GPP_H21, 0, DEEP), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 0, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +#endif + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h new file mode 100644 index 0000000..190474f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _HDA_VERB_H_ +#define _HDA_VERB_H_ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID: 0x10EC119E */ + 0x0017209E, + 0x00172111, + 0x001722EC, + 0x00172310, + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x02ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x022b1010), + /* ONE DOES NOT SIMPLY + MAKE IT WORK WITH WINDOWS */ + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c new file mode 100644 index 0000000..389a91c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <gpio.h> +#include <string.h> +#include <types.h> + +#include "baseboard/memory.h" + +u8 get_memory_config_straps(void) +{ + /* + * The hardware supports a number of different memory configurations + * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6), + * ID1 (GPP_E23) and ID0 (GPP_E22). + * + * The mapping is defined in the schematics as follows ID3 is always + * 0 and can be ignored): + * + * ID2ID1ID0Memory type + * -------------------- + * 1 1 1 Samsung 4G single channel + * 1 1 0 Samsung 8G dual channel + * 1 0 1 Micron 4G single channel + * 1 0 0 Micron 8G dual channel + * 0 1 1 Hynix 4G single channel + * 0 1 0 Hynix 8G dual channel + * 0 0 1 Micron 16G dual channel + * 0 0 0 Hynix 16G dual channel + * + * We return the value of these bits so that the index into the SPD + * table can be .spd[] values can be configured correctly in the + * memory configuration structure. + */ + + gpio_t memid_gpios[] = { + GPP_E22, + GPP_E23, + GPP_H6 + }; + return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios)); +} + +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + u8 memid; + + struct cnl_mb_cfg std_memcfg = { + /* + * The dqs_map arrays map the DDR4 pins to the SoC pins + * for both channels. + * + * the index = pin number on DDR4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 6, 1, 3, 5, 2, 7, 4}, + .dqs_map[DDR_CH1] = {7, 5, 3, 6, 2, 4, 0, 1}, + + /* + * Mainboard uses 121, 81 and 100 rcomp resistors. See R6E1, R6E2 + * and R6E3 on page 6 of the schematics. + */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Mainboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* + * Mainboard is a non-interleaved design - see pages 5 & 6 + * of the schematics. + */ + .dq_pins_interleaved = 0, + + /* + * Mainboard is using DDR_VREF_CA for CH_A and DDR1_VREF_DQ for + * CH_B - see page 5 of the schematics. + */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, + }; + + memcpy(mem_cfg, &std_memcfg, sizeof(std_memcfg)); + + memid = get_memory_config_straps(); + printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid); + + /* + * If we are using single channel ID = 3, 5 or 7 then we only + * populate .spd[0].If we are dual channel then we also populate + * .spd[2] as well. + */ + mem_cfg->spd[0].read_type = READ_SPD_CBFS; + mem_cfg->spd[0].spd_spec.spd_index = memid; + if (memid != 3 && memid != 5 && memid != 7) { + mem_cfg->spd[2].read_type = READ_SPD_CBFS; + mem_cfg->spd[2].spd_spec.spd_index = memid; + } + + return mem_cfg; +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg board_memcfg; + + const uint8_t vtd = get_uint_option("vtd", 1); + memupd->FspmTestConfig.VtdDisable = !vtd; + const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; + + cannonlake_memcfg_init(&memupd->FspmConfig, get_memory_cfg(&board_memcfg)); +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc new file mode 100644 index 0000000..e04a8db --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd new file mode 100644 index 0000000..08bc519 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd @@ -0,0 +1,13 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 8M { + BIOS@0x200000 0x600000 { + RW_MRC_CACHE@0x0 0x10000 + SMMSTORE@0x10000 0x40000 + CONSOLE@0x50000 0x20000 + FMAP@0x70000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt new file mode 100644 index 0000000..b7146c5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb new file mode 100644 index 0000000..d052352c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb @@ -0,0 +1,203 @@ +chip soc/intel/skylake + # Disable DEEP + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # Enable "Intel Speed Shift Technology" + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + # register "SendVrMbxCmd" = "2" + +# Graphics (soc/intel/skylake/graphics.c) + register "panel_cfg" = "{ + .up_delay_ms= 200,// T3 + .down_delay_ms= 0,// T10 + .cycle_delay_ms = 500,// T12 + .backlight_on_delay_ms=50,// T7 + .backlight_off_delay_ms = 0,// T9 + .backlight_pwm_hz = 200, + }" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# CPU (soc/intel/skylake/chip.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0]= PchSerialIoPci, + [PchSerialIoIndexI2C1]= PchSerialIoPci, + [PchSerialIoIndexI2C2]= PchSerialIoPci, + [PchSerialIoIndexI2C3]= PchSerialIoPci, + [PchSerialIoIndexI2C4]= PchSerialIoDisabled, + [PchSerialIoIndexI2C5]= PchSerialIoPci, + [PchSerialIoIndexSpi0]= PchSerialIoPci, + [PchSerialIoIndexSpi1]= PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # Power + register "PmConfigSlpS3MinAssert" = "3" # 50ms + register "PmConfigSlpS4MinAssert" = "3" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "5" + +# PM Util (soc/intel/skylake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_C" + register "gpe0_dw2" = "GPP_E" + + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal Device + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # uSD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Actual Bluetooth port + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "0" + register "SataMode" = "0" + + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "0" + + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "0" + end + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #4 + device pci 19.2 off end # I2C #5 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + register "PcieRpLtrEnable[5]" = "1" + chip drivers/wifi/generic + device pci 00.0 on end + end + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9(SSD x4) + device pci 00.0 on end + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" + register "PcieRpClkSrcNumber[8]" = "0" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00000069" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x0000006d" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + subsystemid 0x10ec 0x111e + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h new file mode 100644 index 0000000..803007d --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_GPIO_H_ +#define _VARIANT_GPIO_H_ + +#include "baseboard/variants.h" + +#ifndef __ACPI__ + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD2, 0x04000300, 0x1000), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD7, 0x04000101, 0x1000), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPI(GPD9, DN_20K, PWROK), + PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1), + PAD_CFG_NF(GPD11, DN_20K, PWROK, NF1), + PAD_NC(GPP_A0, NONE), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_NC(GPP_A10, DN_20K), + PAD_CFG_GPI(GPP_A11, DN_20K, DEEP), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, DN_20K), + PAD_NC(GPP_A14, DN_20K), + PAD_NC(GPP_A15, DN_20K), + PAD_NC(GPP_A16, DN_20K), + PAD_NC(GPP_A17, DN_20K), + PAD_NC(GPP_A18, DN_20K), + PAD_NC(GPP_A19, DN_20K), + PAD_NC(GPP_A20, DN_20K), + PAD_NC(GPP_A21, DN_20K), + PAD_NC(GPP_A22, DN_20K), + PAD_NC(GPP_A23, DN_20K), + PAD_NC(GPP_B0, DN_20K), + PAD_NC(GPP_B1, DN_20K), + PAD_NC(GPP_B2, DN_20K), + PAD_NC(GPP_B3, DN_20K), + PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_B6, DN_20K, DEEP), + PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1), + PAD_NC(GPP_B11, DN_20K), + PAD_NC(GPP_B12, DN_20K), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_NC(GPP_B14, DN_20K), + PAD_NC(GPP_B15, DN_20K), + PAD_NC(GPP_B16, DN_20K), + PAD_NC(GPP_B17, DN_20K), + PAD_NC(GPP_B18, DN_20K), + PAD_NC(GPP_B19, DN_20K), + PAD_NC(GPP_B20, DN_20K), + PAD_NC(GPP_B21, DN_20K), + PAD_NC(GPP_B22, DN_20K), + PAD_NC(GPP_B23, DN_20K), + PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1), + PAD_NC(GPP_C2, DN_20K), + PAD_NC(GPP_C3, DN_20K), + PAD_NC(GPP_C4, DN_20K), + PAD_NC(GPP_C5, DN_20K), + PAD_NC(GPP_C6, DN_20K), + PAD_NC(GPP_C7, DN_20K), + PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000), + PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1), + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_NC(GPP_C22, NONE), + _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x3000), + PAD_NC(GPP_D0, DN_20K), + PAD_NC(GPP_D1, DN_20K), + PAD_NC(GPP_D2, DN_20K), + PAD_NC(GPP_D3, DN_20K), + PAD_NC(GPP_D4, DN_20K), + PAD_NC(GPP_D5, DN_20K), + PAD_NC(GPP_D6, DN_20K), + PAD_NC(GPP_D7, DN_20K), + PAD_NC(GPP_D8, DN_20K), + PAD_NC(GPP_D9, DN_20K), + PAD_NC(GPP_D10, DN_20K), + PAD_NC(GPP_D11, DN_20K), + PAD_NC(GPP_D12, DN_20K), + PAD_NC(GPP_D13, DN_20K), + PAD_NC(GPP_D14, DN_20K), + PAD_NC(GPP_D15, DN_20K), + PAD_NC(GPP_D16, DN_20K), + PAD_NC(GPP_D17, DN_20K), + PAD_NC(GPP_D18, DN_20K), + PAD_NC(GPP_D19, DN_20K), + PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP), + PAD_NC(GPP_D21, DN_20K), + PAD_NC(GPP_D22, DN_20K), + PAD_NC(GPP_D23, DN_20K), + PAD_NC(GPP_E0, DN_20K), + PAD_NC(GPP_E1, DN_20K), + _PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000), + PAD_NC(GPP_E3, DN_20K), + PAD_NC(GPP_E4, DN_20K), + PAD_NC(GPP_E5, DN_20K), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, DN_20K), + PAD_NC(GPP_E8, DN_20K), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, DN_20K), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0000), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_NC(GPP_E20, DN_20K), + PAD_NC(GPP_E21, DN_20K), + PAD_NC(GPP_E22, DN_20K), + PAD_NC(GPP_E23, DN_20K), + PAD_NC(GPP_F0, DN_20K), + PAD_NC(GPP_F1, DN_20K), + PAD_NC(GPP_F2, DN_20K), + PAD_NC(GPP_F3, DN_20K), + PAD_NC(GPP_F4, DN_20K), + PAD_NC(GPP_F5, DN_20K), + PAD_NC(GPP_F6, DN_20K), + PAD_NC(GPP_F7, DN_20K), + PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F9, DN_20K, DEEP, NF1), + PAD_NC(GPP_F10, DN_20K), + PAD_NC(GPP_F11, DN_20K), + PAD_NC(GPP_F12, DN_20K), + PAD_NC(GPP_F13, DN_20K), + PAD_NC(GPP_F14, DN_20K), + PAD_NC(GPP_F15, DN_20K), + PAD_NC(GPP_F16, DN_20K), + PAD_NC(GPP_F17, DN_20K), + PAD_NC(GPP_F18, DN_20K), + PAD_NC(GPP_F19, DN_20K), + PAD_NC(GPP_F20, DN_20K), + PAD_NC(GPP_F21, DN_20K), + PAD_NC(GPP_F22, DN_20K), + PAD_NC(GPP_F23, DN_20K), + PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G4, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G5, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G6, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G7, DN_20K, DEEP), + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +#endif + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h new file mode 100644 index 0000000..2ad9096 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _HDA_VERB_H_ +#define _HDA_VERB_H_ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC111E */ + 0x0017201E, + 0x00172111, + 0x001722EC, + 0x00172310, + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x15, 0x042B1010), + AZALIA_PIN_CFG(0, 0x17, 0x411111F0), + AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + /* Widget node 0x20 */ + 0x02050018, + 0x02040184, /* Stock: 0x02043984 */ + 0x0205001C, + 0x02040800, + /* Widget node 0x20 - 1 */ + 0x02050024, + 0x02040000, + 0x02050004, + 0x02040080, + /* Widget node 0x20 - 2 */ + 0x02050008, + 0x02040300, + 0x0205000C, + 0x02043F00, + /* Widget node 0x20 - 3 */ + 0x02050015, + 0x02048002, + 0x02050015, + 0x02048002, + /* Widget node 0x0C */ + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c new file mode 100644 index 0000000..4f1b7e0 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd_util.c" +#include "spd/spd.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + /* Use the correct entry in the SPD table defined in Makefile.inc */ + u8 spd_index = 6; + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + /* Memory leak is ok since we have memory mapped boot media */ + // TODO evaluate google/eve way of loading + mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); + if (!mem_cfg->MemorySpdPtr00) + die("spd.bin not found\n"); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 15 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... ec: Add Star Labs ITE 8987E support Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52797 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/ec/starlabs/it8987/Kconfig A src/ec/starlabs/it8987/Makefile.inc A src/ec/starlabs/it8987/acpi/ac.asl A src/ec/starlabs/it8987/acpi/battery.asl A src/ec/starlabs/it8987/acpi/cmos.asl A src/ec/starlabs/it8987/acpi/ec.asl A src/ec/starlabs/it8987/acpi/hid.asl A src/ec/starlabs/it8987/acpi/keyboard.asl A src/ec/starlabs/it8987/acpi/lid.asl A src/ec/starlabs/it8987/acpi/thermal.asl A src/ec/starlabs/it8987/chip.h A src/ec/starlabs/it8987/ec.c A src/ec/starlabs/it8987/ec.h 13 files changed, 1,083 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/starlabs/it8987/Kconfig b/src/ec/starlabs/it8987/Kconfig new file mode 100644 index 0000000..ba9e908 --- /dev/null +++ b/src/ec/starlabs/it8987/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_STARLABS_IT8987 + bool + select EC_ACPI + help + Interface to IT8987 embedded controller principally in Star Labs notebooks. diff --git a/src/ec/starlabs/it8987/Makefile.inc b/src/ec/starlabs/it8987/Makefile.inc new file mode 100644 index 0000000..b021d0f --- /dev/null +++ b/src/ec/starlabs/it8987/Makefile.inc @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only + +PHONY+=add_ite_fw +INTERMEDIATE+=add_ite_fw + +ifeq ($(CONFIG_EC_STARLABS_IT8987),y) +all-y += ec.c +smm-$(CONFIG_DEBUG_SMI) += ec.c +endif + +ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN),y) + +ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN_PATH),) +files_added:: warn_no_ite_fw +endif + +add_ite_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_IT8987_BIN_PATH) -u +endif + +PHONY+=warn_no_ite_fw +warn_no_ite_fw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the IT8987 EC Firmware.\n" + printf "Do not flash this image. Your LabTop Mk IV's power button\n" + printf "may not respond when you press it.\n\n" diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl new file mode 100644 index 0000000..97ae147 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/ac.asl @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (ECON == 1) + { + Local0 = 0x0F + } + Else + { + Local0 = 0 + } + Return (Local0) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If (ECWR & 0x01) + { + \PWRS = 1 + } + Else + { + \PWRS = 0 + } + Return (\PWRS) + } +} + +Method (_QA0, 0, NotSerialized) // AC Power Connected +{ + If (ECWR & 0x01) + { + \PWRS = 1 + } + Else + { + \PWRS = 0 + } + + // 500ms delay - Not used in coreboot + // Sleep (500) + Notify (BAT0, 0x81) + // Sleep (500) + Notify (ADP1, 0x80) +} + +Method(_Q0B, 0, NotSerialized) // Battery Connected +{ + // 500ms delay - Not used in coreboot + // Sleep (500) + Notify (BAT0, 0x81) + // Sleep (500) + Notify (BAT0, 0x80) +} diff --git a/src/ec/starlabs/it8987/acpi/battery.asl b/src/ec/starlabs/it8987/acpi/battery.asl new file mode 100644 index 0000000..8936701 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/battery.asl @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + // Battery Slot Status + Method (_STA, 0, Serialized) + { + If (ECWR & 0x02) + { + Return (0x1F) + } + Return (0x0F) + } + + // Default Static Battery Information + Name (BPKG, Package (13) + { + 1, // 0: Power Unit + 0xFFFFFFFF, // 1: Design Capacity + 0xFFFFFFFF, // 2: Last Full Charge Capacity + 1, // 3: Battery Technology(Rechargeable) + 0xFFFFFFFF, // 4: Design Voltage 10.8V + 0, // 5: Design capacity of warning + 0, // 6: Design capacity of low + 0x64, // 7: Battery capacity granularity 1 + 0, // 8: Battery capacity granularity 2 + "CN6613-2S3P", // 9: Model Number + "6UA3", // 10: Serial Number + "Real", // 11: Battery Type + "GDPT" // 12: OEM Information + }) + + Method (_BIF, 0, Serialized) + { + BPKG[1] = B1DC + BPKG[2] = B1FC + BPKG[4] = B1FV + If (B1FC) + { + BPKG[5] = B1FC / 10 + BPKG[6] = B1FC / 25 + BPKG[7] = B1DC / 100 + } + + Return (BPKG) + } + + Name (PKG1, Package (4) + { + 0xFFFFFFFF, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + + Method (_BST, 0, Serialized) + { + + + PKG1[0] = B1ST & 0x07 + If (B1ST & 0x01) + { + PKG1[1] = B1CR + } + Else + { + PKG1[1] = B1CR + } + PKG1[2] = B1RC + PKG1[3] = B1VT + Return (PKG1) + } +} diff --git a/src/ec/starlabs/it8987/acpi/cmos.asl b/src/ec/starlabs/it8987/acpi/cmos.asl new file mode 100644 index 0000000..052094c --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/cmos.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (CMOS, SystemIO, 0x70, 0x02) +Field (CMOS, ByteAcc, NoLock, Preserve) +{ + NVRI, 8, + NVRD, 8 +} + +IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve) +{ + Offset (0x40), + KBBL, 8, // Keyboard backlight timeout + FNSW, 8, // Ctrl Fn Reverse (make keyboard Apple-like) + + Offset (0x7D), + FNLC, 8 // Current state of Fn Lock key. +} diff --git a/src/ec/starlabs/it8987/acpi/ec.asl b/src/ec/starlabs/it8987/acpi/ec.asl new file mode 100644 index 0000000..451cdf1 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/ec.asl @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ASL_PVOL_DEFOF_NUM 0xe8 + +Scope(\) +{ + // These fields come from the Global NVS area + Field (GNVS,AnyAcc,Lock,Preserve) + { + Offset(33), + B2SC, 8, // (33) Battery 2 Stored Capacity + Offset(36), + B2SS, 8 // (36) Battery 2 Stored Status + } +} + +Scope (\_SB) +{ + #include "hid.asl" +} + +Scope (\_SB.PCI0) +{ + // Add the entries for the PS/2 keyboard and mouse. + #include <drivers/pc80/pc/ps2_controller.asl> +} + +Scope (\_SB.PCI0.LPCB) +{ + // Include the definitions for accessing CMOS. + #include "cmos.asl" + + // Our embedded controller device. + Device (H_EC) + { + Name (_HID, EISAID ("PNP0C09")) // ACPI Embedded Controller + Name (_UID, 1) + Name (_GPE, EC_GPE_SCI) + + // ECDT (Embedded Controller Boot Resources Table) Check to correct + // ECAV flag in the beginning + Name(ECTK, 1) + Name(ECFG, 0) + Name(WIBT, 0) + Name(APST, 0) + + Name(ECON, 1) // AC debug + Name(BNUM, 0) // Number Of Batteries Present + Name(PVOL, ASL_PVOL_DEFOF_NUM) + Name(B1CC, 0) + Name(B2CC, 0) + + Name(B2ST, 0) + Name(CFAN, 0) + Name(CMDR, 0) + Name(DOCK, 0) + Name(EJET, 0) + Name(MCAP, 0) + Name(PLMX, 0) + Name(PECH, 0) + Name(PECL, 0) + Name(PENV, 0) + Name(PINV, 0) + Name(PPSH, 0) + Name(PPSL, 0) + Name(PSTP, 0) + Name(RPWR, 0) + Name(LIDS, 0) + Name(SLPC, 0) + Name(VPWR, 0) + Name(WTMS, 0) + Name(AWT2, 0) + Name(AWT1, 0) + Name(AWT0, 0) + Name(DLED, 0) + Name(IBT1, 0) + Name(ECAV, 1) // Support DPTF feature + Name(SPT2, 0) + Name(PB10, 0) + Name(IWCW, 0) + Name(IWCR, 0) + Name(BTEN, 0) + Mutex(ECMT, 0) + + Method (_CRS, 0, Serialized) + { + Name (BFFR, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0x00, 0x01) + IO (Decode16, 0x66, 0x66, 0x00, 0x01) + }) + Return (BFFR) + } + + Method (_STA, 0, NotSerialized) + { + If ((ECON == 1)) + { + Return (0x0F) + } + + Return (0x00) + } + + Name (ECOK, Zero) + Method(_REG, 2, NotSerialized) + { + If ((Arg0 == 0x03) && (Arg1 == 0x01)) + { + ECOS = 1 + ECAV = 1 + + // Unconditionally fix up the Battery and Power State. + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + BNUM = 0 + BNUM |= ((ECRD (RefOf (ECWR)) & 0x02) >> 1) + + // Save the current Power State for later. + // Store (PWRS, Local0) + + // Initialize the Power State. + // BNUM = 0 = Virtual Power State + // BNUM > 0 = Real Power State + If (BNUM == 0x00) + { + \PWRS = ECRD (RefOf (VPWR)) + } + Else + { + \PWRS = (ECRD (RefOf (ECWR)) & 0x01) + } + PNOT() + + /* Initialize LID switch state */ + \LIDS = LIDS + } + + // Flag that the OS supports ACPI. + \_SB.PCI0.LPCB.H_EC.ECOS = 1 + } + + Name (S3OS, Zero) + Method (PTS, 1, Serialized) + { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + S3OS = ECOS + } + \_SB.PCI0.LPCB.H_EC.ECOS = 0 + } + + Method (WAK, 1, Serialized) + { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + ECOS = S3OS + } + \_SB.PCI0.LPCB.H_EC.ECOS = 1 + } + + OperationRegion (SIPR, SystemIO, 0xB2, 0x1) + Field (SIPR, ByteAcc, Lock, Preserve) + { + SMB2, 8 + } + + // EC RAM fields + OperationRegion(ECF2, EmbeddedControl, 0, 0xFF) + Field (ECF2, ByteAcc, Lock, Preserve) + { + XXX0, 8, // EC Firmware main- version number. + XXX1, 8, // EC Firmware sub- version number. + XXX2, 8, // EC Firmware test- version number. + + Offset(0x06), + SKID, 8, // SKU ID + + Offset(0x11), + KBCD, 8, // Key / Touch Pad disable/enable bit + ECOS, 8, // Enter OS flag + HDAO, 8, + ECHK, 8, // Hot keys flag + + Offset(0x18), + KLBS, 8, // Keyboard backlight begin. + KLBE, 8, // Keyboard backlight status. + + Offset(0x1A), + KBLT, 8, // Keyboard Backlight Timeout + PWPF, 8, // Power Profile + + Offset(0x1E), + BTHP,8, // Health Battery Percentage + + Offset(0x20), + RCMD, 8, // Same function as IO 66 port to send EC command + RCST, 8, // Report status for the result of command execution + + Offset(0x2C), + FNST, 8, // FN LOCK key status. + + Offset(0x3F), + SFAN, 8, // Set Fan Speed. + BTMP, 16, // Battery Temperature. + BCNT, 16, // Battery Cycle Count. + FRMP, 16, // Fan Current Speed. + + Offset(0x60), + TSR1, 8, // Thermal Sensor Register 1 [CPU VR (IMVP) Temp on RVP] + TSR2, 8, // Thermal Sensor Register 2 [Heat exchanger fan temp on RVP] + TER4, 8, // Thermal Sensor Register 3 (skin temperature) + + Offset(0x63), + TSI,4, // [0..3] 0 = SEN1 - CPU VR temperature sensor + // 1 = SEN2 - Heat Exchanger temperature sensor + // 2 = SEN3 - Skin temperature sensor + // 3 = SEN4 - Ambient temperature sensor + // 4 = SEN5 - DIMM temperature sensor [IR sensor 1 on WSB] + // 5 = SEN6 - not used on RVP + HYST, 4, // [4..7] - Hysteresis in degC. + TSHT, 8, // Thermal Sensor (N) high trip point(set default value =70) + TSLT, 8, // Thermal Sensor (N) low trip point (set default value =70) + TSSR, 8, // TSSR- thermal sensor status register (set bit2 =1) + // BIT0:SEN1 - CPU VR Temp Sensor Trip Flag + // BIT1:SEN2 - Fan Temp Sensor Trip Flag + // BIT2:SEN3 - Skin Temp Sensor Trip Flag + // BIT3:SEN4 - Ambient Temp Sensor Trip Flag + // BIT4:Reserved + // BIT5:Reserved + // BIT6:Reserved + // BIT7:Reserved + CHGR, 16, // Charge Rate + + Offset(0x70), + CPTM, 8, // CPU Temperature + + Offset(0x72), + TER2, 8, // Charger Temperature, Charger thermistor support + + Offset(0x7F), + LSTE, 1, // Lid feature + // BIT0LID GPI + , 7, // Reserved + + Offset(0x80), + ECWR, 8, // AC & Battery status + XX10, 8, // Battery#1 Model Number Code + XX11, 16, // Battery#1 Serial Number + B1DC, 16, // Battery#1 Design Capacity + B1FV, 16, // Battery#1 Design Voltage + B1FC, 16, // Battery#1 Last Full Charge Capacity + XX15, 16, // Battery#1 Trip Point + B1ST, 8, // Battery#1 State + B1CR, 16, // Battery#1 Present Rate + B1RC, 16, // Battery#1 Remaining Capacity + B1VT, 16, // Battery#1 Present Voltage + BPCN, 8, // Battery#1 Remaining percentage + + // USB Type C Mailbox Interface// PPM->OPM Message In + Offset(0xc0), + MGI0, 8, + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + + // USB Type C Mailbox Interface// OPM->PPM Message Out + MGO0, 8, + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + + // USB Type C UCSI DATA Structure. + VER1, 8, + VER2, 8, + RSV1, 8, + RSV2, 8, + + // PPM->OPM CCI indicator + CCI0, 8, + CCI1, 8, + CCI2, 8, + CCI3, 8, + + // OPM->PPM Control message + CTL0, 8, + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + + Offset(0xF0), + , 3,// BIT0 .. BIT2 Reserved + TPCC, 1,// BIT3 TypeC connection bit + , 2,// BIT4 .. BIT5 Reserved + DRMD, 1,// Bit6 Dual Role Mode. 0->DFP: Host mode; 1->UFP: Device Mode. + , 1,// BIT7 Reserved + } + + Method (ECMD, 0, Serialized) + { + } + + Method (ECWT, 2, Serialized,,, {IntObj, FieldUnitObj}) + { + Local0 = Acquire (ECMT, 1000) + If (Local0 == 0x00) + { + If (ECAV) + { + // Execute write to Embedded Controller + Arg1 = Arg0 + } + Release (ECMT) + } + } + + Method (ECRD, 1, Serialized, 0, IntObj, FieldUnitObj) + { + Local0 = Acquire (ECMT, 1000) + If (Local0 == 0) + { + If (ECAV) + { + // Execute read from Embedded Controller + Local1 = DerefOf (Arg0) + Release (ECMT) + Return (Local1) + } + Else + { + Release (ECMT) + } + } + Return (Local1) + } + + // Include the other parts of the Embedded Controller ASL. + #include "keyboard.asl" + #include "battery.asl" + #include "ac.asl" + #include "lid.asl" + + // Method(_Q45) // SMM Mode - Not used in coreboot + // { + // SMB2 = 0xC1 + // } + } +} diff --git a/src/ec/starlabs/it8987/acpi/hid.asl b/src/ec/starlabs/it8987/acpi/hid.asl new file mode 100644 index 0000000..25e3cd2 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/hid.asl @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HMDE, Zero) + Name (HRDY, Zero) + Name (BTLD, Zero) + Name (BTS1, Zero) + Name (HEB1, 0x3003) + + Method (_STA, 0, Serialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + + Method (HDDM, 0, Serialized) + { + Store ("-----> HDDM", Debug) + Name (DPKG, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Return (DPKG) + } + + Method (HDEM, 0, Serialized) + { + Store ("-----> HDEM", Debug) + HBSY = Zero + If ((HMDE == Zero)) + { + Return (HIDX) + } + Return (HMDE) + } + + Method (HDMM, 0, Serialized) + { + Store ("-----> HDMM", Debug) + Return (HMDE) + } + + Method (HDSM, 1, Serialized) + { + Store ("-----> HDSM", Debug) + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + Store ("-----> HPEM", Debug) + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While ((Local0 < 0xFA) && HBSY) + { + Sleep (0x04) + Local0++ + } + + If (HBSY == One) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } + + Method (BTNL, 0, Serialized) + { + Store ("-----> BTNL", Debug) + If (CondRefOf (\_SB.PWRB.PBST)) + { + \_SB.PWRB.PBST = Zero + Notify (PWRB, One) // Device Check + } + + BTLD = One +// If ((AEAB == One)) +// { + BTS1 = 0x1F + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } +// Else +// { +// BTS1 = Zero +// } + } + + Method (BTNE, 1, Serialized) + { + Store ("-----> BTNE", Debug) +// If ((AEAB == One)) +// { + BTS1 = ((Arg0 & 0x1E) | One) + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } + } + + Method (BTNS, 0, Serialized) + { + Store ("-----> BTNS", Debug) +// If ((AEAB == One)) +// { + BTS1 = \_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } + Return (BTS1) + } + + Method (BTNC, 0, Serialized) + { + Store ("-----> BTNC", Debug) +// If ((AEAB == One)) +// { + Return (0x1F) +// } +// Else +// { +// Return (Zero) +// } + } + + Name (HEB2, Zero) + Method (HEBC, 0, Serialized) + { + Store ("-----> HEBC", Debug) +// If ((AHDB == One)) +// { +// Return (\HEB1) +// } +// Else +// { + Return (Zero) +// } + } + + Method (H2BC, 0, Serialized) + { + Store ("-----> H2BC", Debug) +// If ((AHDB == One)) +// { +// Return (\HEB1) +// } +// Else +// { + Return (Zero) +// } + } + + Method (HEEC, 0, Serialized) + { + Store ("-----> HEEC", Debug) +// If ((AHDB == One)) +// { + Return (HEB2) /* \_SB_.HIDD.HEB2 */ +// } +// Else +// { +// Return (Zero) +// } + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("eeec56b3-4442-408f-a792-4edd4d758054"))) + { + If ((One == ToInteger (Arg1))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x03 + }) + } + Case (One) + { + BTNL () + } + Case (0x02) + { + Return (HDMM ()) + } + Case (0x03) + { + HDSM (DerefOf (Arg3 [Zero])) + } + Case (0x04) + { + Return (HDEM ()) + } + Case (0x05) + { + Return (BTNS ()) + } + Case (0x06) + { + BTNE (DerefOf (Arg3 [Zero])) + } + Case (0x07) + { + Return (HEBC ()) + } + Case (0x08) + { + } + Case (0x09) + { + Return (H2BC ()) + } + } + } + } + + Return (Buffer (One) + { + 0x00 + }) + } +} + +Method (PWPR, 0, Serialized) +{ + Notify (HIDD, 0xCE) +} + +Method (PWRR, 0, Serialized) +{ + Notify (HIDD, 0xCF) +} diff --git a/src/ec/starlabs/it8987/acpi/keyboard.asl b/src/ec/starlabs/it8987/acpi/keyboard.asl new file mode 100644 index 0000000..f5b1d52 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/keyboard.asl @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_Q80) // Volume up +{ + Store ("-----> _Q80", Debug) + Notify (\_SB.HIDD, 0xC4) + Notify (\_SB.HIDD, 0xC5) + Store ("<----- _Q80", Debug) +} + +Method(_Q81) // Volume down +{ + Store ("-----> _Q81", Debug) + Notify (\_SB.HIDD, 0xC6) + Notify (\_SB.HIDD, 0xC7) + Store ("<----- _Q81", Debug) +} + +Method(_Q99) // Wireless mode +{ + Store ("-----> _Q99", Debug) + \_SB.HIDD.HPEM(8) + Store ("<----- _Q80", Debug) +} + +Method(_Q06) // Brightness decrease +{ + \_SB.PCI0.GFX0.DECB() +} + +Method(_Q07) // Brightness increase +{ + \_SB.PCI0.GFX0.INCB() +} + +Method(_Q08) // FN lock QEvent +{ + FNLC = FNST +} + +Method(_Q54) // Power Button Event +{ + Store ("-----> _Q54", Debug) + If (CondRefOf (\_SB.PWRB)) + { + Notify(\_SB.PWRB, 0x80) + } + Store ("<----- _Q54", Debug) +} + +Method(_QD5) // 10 second power button press +{ + Store ("-----> _QD5", Debug) + \_SB.PWPR() + Store ("<----- _QD5", Debug) +} + +Method(_QD6) // 10 second power button de-press +{ + Store ("-----> _QD6", Debug) + \_SB.PWRR() + Store ("<----- _QD6", Debug) +} diff --git a/src/ec/starlabs/it8987/acpi/lid.asl b/src/ec/starlabs/it8987/acpi/lid.asl new file mode 100644 index 0000000..22e8eeb --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/lid.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA, 0, NotSerialized) + { + DEBUG = "---> IT8987 LID: _STA" + Return (0x0F) + } + + Method (_PSW, 1, NotSerialized) + { + DEBUG = Concatenate ("---> IT8987 LID: _PSW", ToHexString(Arg0)) + } + + Method (_LID, 0, NotSerialized) + { + DEBUG = "---> IT8987 LID: _LID" + If (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.LSTE)) == 0x01) + { + Local0 = 1 + } + else + { + Local0 = 0 + } + Return (Local0) + } +} + +Method (_Q0C, 0, NotSerialized) // Lid close event +{ + DEBUG = "---> IT8987 LID: Q0C (close event)" + LIDS = 0 + \LIDS = LIDS + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Lid open event +{ + DEBUG = "---> IT8987 LID: Q0D (open event)" + LIDS = 1 + \LIDS = LIDS + Notify (LID0, 0x80) +} diff --git a/src/ec/starlabs/it8987/acpi/thermal.asl b/src/ec/starlabs/it8987/acpi/thermal.asl new file mode 100644 index 0000000..6bf25bf --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_QF0) // Thermal event. +{ + If (LEqual (DBGS, 0x00)) + { + /* Only handle the numerous thermal events if we are */ + /* NOT doing ACPI Debugging. */ + If (CondRefOf (\_TZ.TZ01)) + { + Notify (\_TZ.TZ01, 0x80) + } + } +} diff --git a/src/ec/starlabs/it8987/chip.h b/src/ec/starlabs/it8987/chip.h new file mode 100644 index 0000000..a940a46 --- /dev/null +++ b/src/ec/starlabs/it8987/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EC_STARLABS_IT8987_CHIP_H +#define _EC_STARLABS_IT8987_CHIP_H + +struct ec_starlabs_it8987_config { + u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ +}; + +#endif /* _EC_STARLABS_IT8987_CHIP_H */ diff --git a/src/ec/starlabs/it8987/ec.c b/src/ec/starlabs/it8987/ec.c new file mode 100644 index 0000000..b555d28 --- /dev/null +++ b/src/ec/starlabs/it8987/ec.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> +#include <delay.h> +#include <option.h> + +#include "ec.h" +#include "chip.h" + +u16 it8987_get_version(void) +{ + return (ec_read(0x00) << 8) | ec_read(0x01); +} + +static void it8987_init(struct device *dev) +{ + if (!dev->enabled) + return; + + /* + * The address/data IO port pair for the IT8987 EC are configurable + * through the EC domain and are fixed by the EC's firmware blob. If + * the value(s) passed through the "dev" structure don't match the + * expected values then output severe warnings. + */ + if (dev->path.pnp.port != IT8987E_FIXED_ADDR) { + printk(BIOS_ERR, "IT8987: Incorrect ports defined in devicetree.cb.\n"); + printk(BIOS_ERR, "IT8987: Serious operational issues will arise.\n"); + return; + } + + u8 chipid1 = pnp_read_index(dev->path.pnp.port, IT8987_CHIPID1); + u8 chipid2 = pnp_read_index(dev->path.pnp.port, IT8987_CHIPID2); + if (chipid1 != IT8987_CHIPID1_VAL || chipid2 != IT8987_CHIPID2_VAL) { + printk(BIOS_DEBUG, "IT8987: Device not found.\n"); + return; + } + + printk(BIOS_DEBUG, "IT8987: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + + /* Enable the keyboard backlight support. */ + ec_write(0x18, 0xaa); + ec_write(0x19, 0xdd); + + /* Set the timeout for the keyboard backlight. */ + ec_write(ECRAM_KBL_TIMEOUT, get_uint_option("kbl_timeout", 0)); + + /* + * Set the correct state for the Ctrl Fn Reverse option. This + * swaps the Ctrl and Fn keys to make it like an Apple keyboard. + */ + ec_write(ECRAM_FN_CTRL_REVERSE, get_uint_option("fn_ctrl_swap", 0)); + /* + * Copy the stored state of the fn_lock_state CMOS variable to the + * corresponding location within the EC RAM. + */ + ec_write(ECRAM_FN_LOCK_STATE, get_uint_option("fn_lock_state", 0)); +} + +static struct device_operations ops = { + .init = it8987_init, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_starlabs_it8987_ops = { + CHIP_NAME("ITE IT8987 EC") + .enable_dev = enable_dev +}; diff --git a/src/ec/starlabs/it8987/ec.h b/src/ec/starlabs/it8987/ec.h new file mode 100644 index 0000000..c6d5a7a --- /dev/null +++ b/src/ec/starlabs/it8987/ec.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE IT8987 Embedded Controller. + */ + +#ifndef _EC_STARLABS_IT8987_H +#define _EC_STARLABS_IT8987_H + +/* + * Define the expected value of the PNP base address that is fixed through + * the BADRSEL register controlled within the EC domain by the binary blob. + */ +#define IT8987E_FIXED_ADDR 0x4e + +/* Logical device number (LDN) assignments. */ +#define IT8987E_SP1 0x01 /* Com1 */ +#define IT8987E_SP2 0x02 /* Com2 */ +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + +/* Host domain registers. */ +#define IT8987_CHIPID1 0x20 /* Device ID register 1 */ +#define IT8987_CHIPID2 0x21 /* Device ID register 2 */ + +/* IT8987 chip ID byte values. */ +#define IT8987_CHIPID1_VAL 0x89 +#define IT8987_CHIPID2_VAL 0x87 + +/* EC RAM offsets. */ +#define ECRAM_KBL_TIMEOUT 0x07 +#define ECRAM_FN_CTRL_REVERSE 0x08 +#define ECRAM_FN_LOCK_STATE 0x2C + +u16 it8987_get_version(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 14 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: V Sowmya, Cliff Huang, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 7: (2 comments) Patchset: PS7: Also needs a rebase File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/38a62392_7ec30948 PS7, Line 16: 1536 > Hi Tim, I am getting asl compilation error if I don't use this define as hardcoded value directly. […] Ah ok, that's fine, I wasn't sure if IASL would be able to deal with that or not, thanks for checking! -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021