coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/starlabs/labtop: Unbreak master
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55231 ) Change subject: mb/starlabs/labtop: Unbreak master ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/starlabs/labtop/mainboard.c: https://review.coreboot.org/c/coreboot/+/55231/comment/fc891363_8e8a38df PS1, Line 81: smbios_chassis_asset_tag comment should be updated too? (or just dropped) -- To view, visit https://review.coreboot.org/c/coreboot/+/55231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Gerrit-Change-Number: 55231 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:51:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Unbreak master
by Michael Niewöhner (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55231 ) Change subject: mb/starlabs/labtop: Unbreak master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Gerrit-Change-Number: 55231 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:51:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: V Sowmya, Cliff Huang, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55127 to look at the new patch set (#8). Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in This change adds S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, two kernel changes are also required: https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method needs to implemented in coreboot for PMC requirement register. Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mb/dell: Add OptiPlex 7020 SFF port
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Martin Roth, Angel Pons, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232 ) Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ...................................................................... Patch Set 1: (727 comments) File src/mainboard/dell/optiplex_7020/io.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/60c728f6_b630a401 PS1, Line 14: uint8_t r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8754d44a_3504b12b PS1, Line 15: asm volatile ("inb %1, %0" : "=a"(r) : "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1b1a528d_9571507c PS1, Line 15: asm volatile ("inb %1, %0" : "=a"(r) : "Nd"(port)); Prefer using '"%s...", __func__' to using 'inb', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0a2907ad_e792cdeb PS1, Line 16: return r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ccfe8fd8_1cbafe46 PS1, Line 21: uint16_t r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f343d0f2_368bad31 PS1, Line 22: asm volatile ("inw %1, %0" : "=a"(r) : "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0c18a8c4_256d975f PS1, Line 22: asm volatile ("inw %1, %0" : "=a"(r) : "Nd"(port)); Prefer using '"%s...", __func__' to using 'inw', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b00c1e9b_6f7e1b6b PS1, Line 23: return r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d5b87403_008f7a47 PS1, Line 28: uint32_t r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/71a425f0_4e5de448 PS1, Line 29: asm volatile ("inl %1, %0" : "=a"(r) : "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c045d485_d8e1c3ab PS1, Line 29: asm volatile ("inl %1, %0" : "=a"(r) : "Nd"(port)); Prefer using '"%s...", __func__' to using 'inl', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/278e86f2_bb107a90 PS1, Line 30: return r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a4368278_65eae7a7 PS1, Line 35: asm volatile ("outb %0, %1" : : "a"(val), "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5bdcd267_d90d402b PS1, Line 35: asm volatile ("outb %0, %1" : : "a"(val), "Nd"(port)); Prefer using '"%s...", __func__' to using 'outb', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/23b6165a_1867d6d7 PS1, Line 40: asm volatile ("outw %0, %1" : : "a"(val), "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b976a3d7_d6f35252 PS1, Line 40: asm volatile ("outw %0, %1" : : "a"(val), "Nd"(port)); Prefer using '"%s...", __func__' to using 'outw', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1a7fafba_078f7c1b PS1, Line 45: asm volatile ("outl %0, %1" : : "a"(val), "Nd"(port)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9fa21778_354fd022 PS1, Line 45: asm volatile ("outl %0, %1" : : "a"(val), "Nd"(port)); Prefer using '"%s...", __func__' to using 'outl', this function's name, in a string Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6f9b5ccf_ba4e4fe2 PS1, Line 49: (bus << 16 | dev << 11 | fun << 8 | offs) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ba0de47c_e5b6d773 PS1, Line 53: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/19337b5b_053b6519 PS1, Line 54: return inl(0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/98ad4b5c_5fae8133 PS1, Line 59: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/229c4be7_2fb96844 PS1, Line 60: return inw(0xcfc + (addr & 2)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/40e4c182_1fe80edb PS1, Line 65: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3ebd6c5c_bab8f4bc PS1, Line 66: return inb(0xcfc + (addr & 3)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6cb54270_bdc7b28c PS1, Line 71: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/37591792_b113deab PS1, Line 72: outl(val, 0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/06b82493_0b968c0d PS1, Line 77: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/18469e11_aaa2fcab PS1, Line 78: outw(val, 0xcfc + (addr & 2)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6cb3003a_56cb7bb4 PS1, Line 83: outl(0x80000000 | addr & 0xfffffffc, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/06366bbf_b5b9838c PS1, Line 84: outb(val, 0xcfc + (addr & 3)); please, no spaces at the start of a line File src/mainboard/dell/optiplex_7020/smscprog.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1946a6bf_e2e3548f PS1, Line 27: // Runtime regsiters 'regsiters' may be misspelled - perhaps 'registers'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/99904adf_9eb44530 PS1, Line 37: outb(offset, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/49c2b550_008fc4aa PS1, Line 38: return inb(SMSC_DATA); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ecbaff3e_f7bd34c7 PS1, Line 43: u16 val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3cd58d3c_fe3456b3 PS1, Line 44: val |= smsc_read8(offset); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f89bbdb9_866f9c6f PS1, Line 45: val |= smsc_read8(offset + 1) << 8; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e8bc5d31_82e1a7aa PS1, Line 46: return val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6db0e9fd_bdd5458b PS1, Line 51: u32 val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9225a96f_e81604af PS1, Line 52: val |= smsc_read8(offset); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c37080ef_99ea6b7e PS1, Line 53: val |= smsc_read8(offset + 1) << 8; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/30eaa48c_6efb906e PS1, Line 54: val |= smsc_read8(offset + 2) << 16; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/95ee2517_ac735793 PS1, Line 55: val |= smsc_read8(offset + 3) << 24; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/32e8df85_83a2ab1e PS1, Line 56: return val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9f93e0da_28ba67d0 PS1, Line 61: outb(offset, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9f1c9657_ee3ff38c PS1, Line 62: outb(value, SMSC_DATA); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e7707b96_2552cfdc PS1, Line 67: smsc_write8(offset, value & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3a086680_ec5d2586 PS1, Line 68: smsc_write8(offset + 1, (value >> 8) & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/92c66a0c_e9589150 PS1, Line 73: smsc_write8(offset, value & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b1c280b9_4bd33347 PS1, Line 74: smsc_write8(offset + 1, (value >> 8) & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/51137b59_b92f6cd9 PS1, Line 75: smsc_write8(offset + 2, (value >> 16) & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a12d77fb_61061ed3 PS1, Line 76: smsc_write8(offset + 3, (value >> 24) & 0xff); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/de2bbbd6_5f8f271f PS1, Line 84: WIDTH8, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9e92873b_fda442b1 PS1, Line 85: WIDTH16, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/703eed20_528e23fd PS1, Line 86: WIDTH32 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6993aacd_40a548c1 PS1, Line 90: enum smsc_width width; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/94071508_ac7703f0 PS1, Line 91: u8 offset; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/38e536ea_817d79bb PS1, Line 92: const char *name; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/611ebc97_1beed825 PS1, Line 96: u8 ldn; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b5f6ec37_d9b545b3 PS1, Line 97: const char *name; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/73d808cf_d2fa813b PS1, Line 98: struct smsc_reg *regs; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2c18b54f_b80b19ab PS1, Line 102: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5d1b7dea_92a02706 PS1, Line 103: .ldn = 0x3f, // NOTE: Selecting it is not necessary code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5551b2c9_3a157443 PS1, Line 103: .ldn = 0x3f, // NOTE: Selecting it is not necessary please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/87b391df_246344f5 PS1, Line 104: .name = "Global Configuration ", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8e1908c5_e86e620f PS1, Line 104: .name = "Global Configuration ", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/179a4e58_36e4ff97 PS1, Line 105: .regs = (const struct smsc_reg[]) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/659146f9_d17efadc PS1, Line 105: .regs = (const struct smsc_reg[]) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3ac4289f_8d902346 PS1, Line 106: { WIDTH8, 0x07, "Logical Device Number " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3a9710cd_7aed5156 PS1, Line 106: { WIDTH8, 0x07, "Logical Device Number " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fa6f63a9_4f4200bc PS1, Line 107: { WIDTH8, 0x20, "Device ID " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/61cb2724_97686b0c PS1, Line 107: { WIDTH8, 0x20, "Device ID " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e224d36a_9eaa1bb5 PS1, Line 108: { WIDTH8, 0x21, "Device Revision " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7d27f8ba_419a9c69 PS1, Line 108: { WIDTH8, 0x21, "Device Revision " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a0bdb21f_41a5dc8c PS1, Line 109: { WIDTH8, 0x24, "Device Mode " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fe0125d0_3f928730 PS1, Line 109: { WIDTH8, 0x24, "Device Mode " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5bef3edc_867ddb8f PS1, Line 110: { 0, 0, 0 } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bb94e9d4_59296495 PS1, Line 110: { 0, 0, 0 } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/93090a67_70676949 PS1, Line 111: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7d595c92_7e1ce647 PS1, Line 111: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/69df69df_12b1a717 PS1, Line 112: }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b6cf7e50_6c6d891f PS1, Line 113: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2ad3cbdf_42bfa5a2 PS1, Line 114: .ldn = 0x0c, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ff721a31_68791a66 PS1, Line 114: .ldn = 0x0c, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b9a29e62_e7a218a6 PS1, Line 115: .name = "LPC Interface ", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f2a04512_2709394a PS1, Line 115: .name = "LPC Interface ", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/615674a5_9e28dcfe PS1, Line 116: .regs = (const struct smsc_reg[]) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1b32e63f_742f08da PS1, Line 116: .regs = (const struct smsc_reg[]) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2a268a77_f45e58c5 PS1, Line 117: { WIDTH8, 0x30, "Activate " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9d430a57_14c6be85 PS1, Line 117: { WIDTH8, 0x30, "Activate " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/685e8bc1_b0513d3e PS1, Line 118: { WIDTH32, 0x60, "LPC Interface BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/155dac45_4a152a25 PS1, Line 118: { WIDTH32, 0x60, "LPC Interface BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d3200b06_fb237fe7 PS1, Line 119: { WIDTH32, 0x64, "EMI BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ed79f90e_3f68429c PS1, Line 119: { WIDTH32, 0x64, "EMI BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/79e1dca6_0cc27f35 PS1, Line 120: { WIDTH32, 0x68, "UART1 BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d51310ee_d15020ff PS1, Line 120: { WIDTH32, 0x68, "UART1 BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cd78dd1c_9fd39584 PS1, Line 121: { WIDTH32, 0x6c, "UART2 BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5ab4a5cf_253bb153 PS1, Line 121: { WIDTH32, 0x6c, "UART2 BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/effa498f_5bc7fbdf PS1, Line 122: { WIDTH32, 0x70, "Runtime Registers BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1db4bb8f_4aae5122 PS1, Line 122: { WIDTH32, 0x70, "Runtime Registers BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7be4142b_261d6ac5 PS1, Line 123: { WIDTH32, 0x74, "Undocumented BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3924fd43_d07c09ce PS1, Line 123: { WIDTH32, 0x74, "Undocumented BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7b6dc53a_f6bf1ad4 PS1, Line 124: { WIDTH32, 0x78, "8042 BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ff0fa62e_296e24c0 PS1, Line 124: { WIDTH32, 0x78, "8042 BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0511146b_54d90711 PS1, Line 125: { WIDTH32, 0x7c, "Floppy Disk Controller BAR" }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9d446d6a_57a8b5d8 PS1, Line 125: { WIDTH32, 0x7c, "Floppy Disk Controller BAR" }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/03ece0e2_eb561bfc PS1, Line 126: { WIDTH32, 0x80, "Parallel Port BAR " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/02329898_5c7e186f PS1, Line 126: { WIDTH32, 0x80, "Parallel Port BAR " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d3049a86_c7557f64 PS1, Line 127: { 0, 0, 0 } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9bef3dc5_85be4b76 PS1, Line 127: { 0, 0, 0 } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1f3f8470_72a3fc8b PS1, Line 128: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e03af3a1_16ae2820 PS1, Line 128: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6a70f1c9_0cef3ea4 PS1, Line 129: }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c4bbc629_11ce87ff PS1, Line 130: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4f627d5c_2c8b64d6 PS1, Line 131: .ldn = 0x07, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c65d5dc1_f2ea3278 PS1, Line 131: .ldn = 0x07, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b9eeba15_39608c68 PS1, Line 132: .name = "UART1 ", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/23af8f4c_d739d6a3 PS1, Line 132: .name = "UART1 ", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8d586122_b4409faf PS1, Line 133: .regs = (const struct smsc_reg[]) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0830bc5b_dc4de166 PS1, Line 133: .regs = (const struct smsc_reg[]) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a6fcc4f2_5f57758d PS1, Line 134: { WIDTH8, 0x30, "Activate " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/efbfa57b_632ef956 PS1, Line 134: { WIDTH8, 0x30, "Activate " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/04dda14e_c4ed64a5 PS1, Line 135: { WIDTH8, 0xf0, "Configuration Select " }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/31a449db_006562b7 PS1, Line 135: { WIDTH8, 0xf0, "Configuration Select " }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8f3f577a_94db801d PS1, Line 136: { 0, 0, 0 } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5fe811d6_03c19e37 PS1, Line 136: { 0, 0, 0 } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/df1da107_8908fa47 PS1, Line 137: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/097010fe_e6595de7 PS1, Line 137: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fc043b74_9ec3d5e8 PS1, Line 138: }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c9cec441_9d4757c1 PS1, Line 139: { 0, 0, 0 } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bde30f9e_e9fcc537 PS1, Line 151: outw(addr | 0x8000, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d03036a6_7b8d52e0 PS1, Line 152: return inb(emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/73277ae4_d5f5c6eb PS1, Line 157: outw(addr | 0x8001, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7101e4a0_eea54262 PS1, Line 158: return inw(emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f2d89115_2927c0d3 PS1, Line 163: outw(addr | 0x8002, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d3355ae1_a2477592 PS1, Line 164: return inl(emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/68e7c3e0_309cadb1 PS1, Line 169: outw(addr | 0x8000, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3f94d581_98665f62 PS1, Line 170: outb(val, emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a25df3f8_488041ea PS1, Line 175: outw(addr | 0x8001, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f97d1841_a287e3ed PS1, Line 176: outw(val, emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cbebcf26_69e734f8 PS1, Line 181: outw(addr | 0x8002, emi_iobase + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/424f5258_d4c0da8c PS1, Line 182: outl(val, emi_iobase + 4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4e55ba74_7f3eee26 PS1, Line 191: inb(emi_iobase + 1); // EC-to-Host Mailbox please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/33b9553a_e85cbedc PS1, Line 192: u8 int_src = inb(emi_iobase + 8) & 0xF6; // Interrupt Source (Byte 0) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6aea1cb7_eccc06bb PS1, Line 193: outb(emi_iobase + 8, int_src); // Clear all Interrupts but 2, clear EC_WR please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/69db1529_50651dd2 PS1, Line 198: u8 int_src; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c1121c99_4e1085f7 PS1, Line 200: outb(val, emi_iobase); // Send value via Host-to-EC mailbox please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/854767b8_0e459f2e PS1, Line 202: do { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7ab8b12d_d430f6d9 PS1, Line 203: int_src = inb(emi_iobase + 8) & 0x71; // 0x71 = 0b1110001 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/63f2452c_62b5953d PS1, Line 203: int_src = inb(emi_iobase + 8) & 0x71; // 0x71 = 0b1110001 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/12d03322_79b598db PS1, Line 204: } while ( !int_src ); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c38e6d63_d4e9f9c7 PS1, Line 204: } while ( !int_src ); space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cfdb700f_316fd87e PS1, Line 204: } while ( !int_src ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fa391634_cdc5e774 PS1, Line 205: outb(int_src, emi_iobase + 8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bee0067a_140b3ad0 PS1, Line 208: if ((int_src & 1) == 0) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a6eef605_dab54461 PS1, Line 209: return 0; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ff694fcf_a20f62ad PS1, Line 209: return 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d0b863b1_366559aa PS1, Line 212: return val == inb(emi_iobase + 1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1befccaa_718e729c PS1, Line 217: u8 int_src = inb(emi_iobase + 0xA); // Save interrupt mask please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/be145f97_810415ed PS1, Line 218: outb(emi_iobase + 0xA, 0); // Mask all interrupts please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f056bc6b_ccfd39dc PS1, Line 219: emi_write16(0, (2 * addr1) | 0x101); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b0c76a46_3078fa6b PS1, Line 220: emi_write32(4, val | (addr2 << 16)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1ca11db7_1eeee89f PS1, Line 221: ec_mailbox_xchg(1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3b87c582_cd7cf560 PS1, Line 222: outb(emi_iobase + 0xA, int_src); // Restore interrupt mask please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fc4a85b4_36e4e640 PS1, Line 227: u8 val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fe5ece89_78016e16 PS1, Line 228: u8 int_src = inb(emi_iobase + 0xA); // save interrupt mask please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0f315554_2f99d84d PS1, Line 229: outb(emi_iobase + 0xA, 0); // mask all interrupts please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/470ffb9b_e2e373a9 PS1, Line 230: emi_write16(0, 2 * (addr1 | 0x80)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5220dd28_33b3607c PS1, Line 231: emi_write32(4, addr2 << 16); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0793e95f_f8b12b55 PS1, Line 232: if (ec_mailbox_xchg(1)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/48ad23be_e72bff65 PS1, Line 232: if (ec_mailbox_xchg(1)) suspect code indent for conditional statements (4, 4) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ddb7d3d2_eb4f3679 PS1, Line 233: val = emi_read8(4); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/75f2c7db_45754d85 PS1, Line 234: outb(emi_iobase + 0xA, int_src); // restore interrupt mask please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/333f8c4c_a868ac41 PS1, Line 235: return val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f191959e_e55c519c PS1, Line 243: u16 addr; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6429f575_94aaf940 PS1, Line 244: u8 val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/11263345_22f718c1 PS1, Line 249: char *r = s1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d780c530_654b196a PS1, Line 250: while (*s2) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3d65919c_2d075e42 PS1, Line 251: *s1++ = *s2++; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1122ba70_cabb6927 PS1, Line 251: *s1++ = *s2++; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1e7b45e6_de2f3128 PS1, Line 252: return r; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f5236510_1c3f9fd8 PS1, Line 257: printk(BIOS_DEBUG, "EC 0xcb: %02x\n", ec_read(1, 0xcb)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/392fad4f_010eb517 PS1, Line 258: printk(BIOS_DEBUG, "EC 0xb8: %02x\n", ec_read(1, 0xb8)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0aed22c9_82c056ea PS1, Line 260: BulkComEnt hwmInitSeq[75]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/94b33d88_52278642 PS1, Line 262: hwmInitSeq[0].addr = 0x2FC; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/422d2d73_242f5c54 PS1, Line 263: hwmInitSeq[1].addr = 0x2FD; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3919ea58_88d33f4e PS1, Line 264: hwmInitSeq[2].addr = 5; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ec0d02ad_b43ec824 PS1, Line 265: hwmInitSeq[3].addr = 0x19; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/26ac18fe_e989f843 PS1, Line 266: hwmInitSeq[4].addr = 0x1A; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6c2af511_14a60c1a PS1, Line 267: hwmInitSeq[5].addr = 0x8A; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0fb6e288_8b211085 PS1, Line 268: hwmInitSeq[6].addr = 0x8B; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d8d6d597_bde87740 PS1, Line 269: hwmInitSeq[7].addr = 0x8C; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ca4448a6_17f17086 PS1, Line 270: hwmInitSeq[8].addr = 0xBA; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d8e2d20f_13be1fc1 PS1, Line 271: hwmInitSeq[9].addr = 0xD1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9264cb95_35dca4b9 PS1, Line 272: hwmInitSeq[10].addr = 0xD6; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4035e5f0_59c80cf6 PS1, Line 273: hwmInitSeq[11].addr = 219; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bc589d37_82b6e9bf PS1, Line 274: hwmInitSeq[13].addr = 73; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/486fed1c_c719e00b PS1, Line 275: hwmInitSeq[14].addr = 122; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dc619bad_41e157fc PS1, Line 276: hwmInitSeq[15].addr = 123; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/98588f02_62a37cac PS1, Line 277: hwmInitSeq[16].addr = 124; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/261b5347_46512502 PS1, Line 278: hwmInitSeq[17].addr = 128; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e71d9252_f3ee445f PS1, Line 279: hwmInitSeq[18].addr = 129; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/06516a2b_29633946 PS1, Line 280: hwmInitSeq[12].addr = 72; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8543e0bf_c7b4c846 PS1, Line 281: hwmInitSeq[19].addr = 130; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4ac015a9_b5d7d8cc PS1, Line 282: hwmInitSeq[20].addr = 131; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/858ec353_6392b817 PS1, Line 283: hwmInitSeq[21].addr = 132; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1b9a9d8a_d022f496 PS1, Line 284: hwmInitSeq[0].val = -96; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c00509ab_02f21736 PS1, Line 285: hwmInitSeq[1].val = 50; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/edfd6b76_1f64fa45 PS1, Line 286: hwmInitSeq[2].val = 119; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b65c06b9_5f8faa85 PS1, Line 287: hwmInitSeq[3].val = 47; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/606a553e_7c7f9caa PS1, Line 288: hwmInitSeq[4].val = 47; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4ff06fd2_83b7d801 PS1, Line 289: hwmInitSeq[5].val = 51; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2deb2169_79508219 PS1, Line 290: hwmInitSeq[6].val = 51; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3702fd47_14b5fd8e PS1, Line 291: hwmInitSeq[7].val = 51; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/412e6255_656a57c0 PS1, Line 292: hwmInitSeq[8].val = 16; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/44c28ba4_3791aa8b PS1, Line 293: hwmInitSeq[9].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6f977adb_f3a7a43e PS1, Line 294: hwmInitSeq[10].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/033046f8_f83e80cd PS1, Line 295: hwmInitSeq[11].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e8654c81_4dcf95a4 PS1, Line 296: hwmInitSeq[12].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/640b4c0f_baefe0b1 PS1, Line 297: hwmInitSeq[13].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e983b99b_f616ce85 PS1, Line 298: hwmInitSeq[14].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7778fecd_32949553 PS1, Line 299: hwmInitSeq[15].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/75b7f8bb_bf0b1522 PS1, Line 300: hwmInitSeq[16].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/07c39b04_ff50e57c PS1, Line 301: hwmInitSeq[17].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6e626cd2_135ca4a4 PS1, Line 302: hwmInitSeq[18].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1b03e66a_d281e436 PS1, Line 303: hwmInitSeq[19].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f259cf02_078c5ed3 PS1, Line 304: hwmInitSeq[20].val = -69; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/11a833c7_4ca6d0f4 PS1, Line 305: hwmInitSeq[21].val = -80; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8c79831d_656da0c0 PS1, Line 306: hwmInitSeq[22].addr = 417; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/274f6a79_5a5549dc PS1, Line 307: hwmInitSeq[22].val = -120; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4cb9ef74_5f24e00e PS1, Line 308: hwmInitSeq[23].addr = 420; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6d0ab2ec_604c17b9 PS1, Line 309: hwmInitSeq[24].addr = 136; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d3592500_d845d2f5 PS1, Line 310: hwmInitSeq[25].addr = 137; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b203d456_bca7dfe7 PS1, Line 311: hwmInitSeq[26].addr = 160; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cf4b411b_2cdec452 PS1, Line 312: hwmInitSeq[27].addr = 161; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7b55119e_545ae283 PS1, Line 313: hwmInitSeq[28].addr = 162; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b5418aba_8ef43121 PS1, Line 314: hwmInitSeq[29].addr = 164; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d1dce393_89757837 PS1, Line 315: hwmInitSeq[30].addr = 165; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f5ab8fe9_a64291db PS1, Line 316: hwmInitSeq[31].addr = 166; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/561a0496_020a4c78 PS1, Line 317: hwmInitSeq[32].addr = 171; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/90bee2ef_25e84ff7 PS1, Line 318: hwmInitSeq[33].addr = 173; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c68266f2_f20d5031 PS1, Line 319: hwmInitSeq[34].addr = 183; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d18f6f9a_478514f7 PS1, Line 320: hwmInitSeq[35].addr = 98; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0d952cc8_78ef579b PS1, Line 321: hwmInitSeq[42].addr = 89; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3c909d16_59bc29a9 PS1, Line 322: hwmInitSeq[43].addr = 97; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9dd08e0c_1fd32ac7 PS1, Line 323: hwmInitSeq[44].addr = 444; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b75642b3_ee591817 PS1, Line 324: hwmInitSeq[45].addr = 445; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4bc89817_143f9546 PS1, Line 325: hwmInitSeq[23].val = 0x80; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/79ab7a78_b8623486 PS1, Line 326: hwmInitSeq[24].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fb688f62_961d5779 PS1, Line 327: hwmInitSeq[25].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/81ca703f_815c3a57 PS1, Line 328: hwmInitSeq[26].val = 2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5d9dc971_ac0a9a72 PS1, Line 329: hwmInitSeq[27].val = 2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a4328d7d_caf7b99c PS1, Line 330: hwmInitSeq[28].val = 2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fb875e21_a7321b5b PS1, Line 331: hwmInitSeq[29].val = 4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7335d956_7814121c PS1, Line 332: hwmInitSeq[30].val = 4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cbc67f34_5743b8c6 PS1, Line 333: hwmInitSeq[31].val = 4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a5546d2f_55e5a44f PS1, Line 334: hwmInitSeq[32].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/495ad923_abc33e26 PS1, Line 335: hwmInitSeq[33].val = 63; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d33270fb_c58904e5 PS1, Line 336: hwmInitSeq[34].val = 7; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/579b4c5c_aa6ae73a PS1, Line 337: strcpy(&hwmInitSeq[35].val, "Pc"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cc290714_b828cb59 PS1, Line 338: strcpy(&hwmInitSeq[36].val, "Fd"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/28402e98_abdeb94c PS1, Line 339: strcpy(&hwmInitSeq[37].val, "Pe"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4f67a788_2bcd5733 PS1, Line 340: strcpy(&hwmInitSeq[38].val, "Ff"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/62cdbf69_f0b2f881 PS1, Line 341: strcpy(&hwmInitSeq[39].val, "Pg"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/506b14bf_a5c521d3 PS1, Line 342: strcpy(&hwmInitSeq[40].val, "FW"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/da119083_334b012a PS1, Line 343: hwmInitSeq[41].val = -104; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3a5522cc_54d6418b PS1, Line 344: hwmInitSeq[42].val = -104; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/df1b33b0_b875108d PS1, Line 345: hwmInitSeq[43].val = 124; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5ea7dc77_9f05f9e4 PS1, Line 346: hwmInitSeq[44].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7a0f9bdb_fdb7595a PS1, Line 347: hwmInitSeq[45].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3ec352c1_d225642c PS1, Line 348: hwmInitSeq[46].addr = 443; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b9aaa5ec_d3d6dc80 PS1, Line 349: hwmInitSeq[46].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/91217d68_34927e6c PS1, Line 350: hwmInitSeq[47].addr = 133; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e191ee43_fd7a253e PS1, Line 351: hwmInitSeq[48].addr = 134; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fa4d03b9_d07f5987 PS1, Line 352: hwmInitSeq[49].addr = 135; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2850fa96_89ff700d PS1, Line 353: hwmInitSeq[50].addr = 144; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/95bc5c55_9dc0b67b PS1, Line 354: hwmInitSeq[51].addr = 145; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b67473bd_d085b49a PS1, Line 355: hwmInitSeq[52].addr = 149; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d0a46d89_0424e8a3 PS1, Line 356: hwmInitSeq[53].addr = 150; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3afa7b0f_d3a02851 PS1, Line 357: hwmInitSeq[54].addr = 151; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cf4a704a_c6559470 PS1, Line 358: hwmInitSeq[55].addr = 155; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b0ad1264_180aa759 PS1, Line 359: hwmInitSeq[56].addr = 174; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a067af21_38070d25 PS1, Line 360: hwmInitSeq[54].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e1668046_0c9e20b4 PS1, Line 361: hwmInitSeq[55].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b21851d8_0e025e3e PS1, Line 362: hwmInitSeq[63].val = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f815cb96_48857e92 PS1, Line 363: hwmInitSeq[57].addr = 175; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2d95d3d0_e43bafc7 PS1, Line 364: hwmInitSeq[58].addr = 179; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/778f9440_e7f0d9b6 PS1, Line 365: hwmInitSeq[64].addr = 691; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0ab5bacb_c8f7d59d PS1, Line 366: hwmInitSeq[59].addr = 196; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5c8fdd9e_59b64a80 PS1, Line 367: hwmInitSeq[65].addr = 692; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2f6c1f69_5765e9f4 PS1, Line 368: hwmInitSeq[66].addr = 716; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6a1c4e3a_10667303 PS1, Line 369: hwmInitSeq[67].addr = 720; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fd30f563_dbb0e009 PS1, Line 370: hwmInitSeq[68].addr = 722; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/efdd0403_48503ad5 PS1, Line 371: hwmInitSeq[59].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6b44745b_549a5711 PS1, Line 372: hwmInitSeq[60].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/756b9c44_d0555f70 PS1, Line 373: hwmInitSeq[61].val = -1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/76f2832c_574857b8 PS1, Line 374: hwmInitSeq[69].addr = 731; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/48869e99_45d93f91 PS1, Line 375: hwmInitSeq[70].addr = 111; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dc79c6d4_af0817f6 PS1, Line 376: hwmInitSeq[60].addr = 197; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bb95efeb_92bac876 PS1, Line 377: hwmInitSeq[71].addr = 112; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b18e1ea2_6141833f PS1, Line 378: hwmInitSeq[47].val = -35; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dfd760da_5a9f9cff PS1, Line 379: hwmInitSeq[48].val = -35; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bd6d6296_1071ef0e PS1, Line 380: hwmInitSeq[49].val = 7; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a1ffc830_c66f6751 PS1, Line 381: hwmInitSeq[50].val = -126; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9535552b_4e439c27 PS1, Line 382: hwmInitSeq[51].val = 94; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/243d33b7_9b498dd2 PS1, Line 383: hwmInitSeq[52].val = 93; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f1357788_a94da282 PS1, Line 384: hwmInitSeq[53].val = -87; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bf250488_4c2765df PS1, Line 385: hwmInitSeq[56].val = -122; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/847b52fb_cabae1b6 PS1, Line 386: hwmInitSeq[57].val = -122; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a888ce07_aeeb7121 PS1, Line 387: hwmInitSeq[58].val = 103; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7a98b714_394b2eab PS1, Line 388: hwmInitSeq[61].addr = 201; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/da2d4ff2_c7c304ce PS1, Line 389: hwmInitSeq[62].addr = 64; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7da7596c_b584f08e PS1, Line 390: hwmInitSeq[62].val = 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/257c9e02_884ca5be PS1, Line 391: hwmInitSeq[63].addr = 0x2FC; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bd5bdaf3_d2630d94 PS1, Line 392: hwmInitSeq[64].val = -102; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f7a2a3dd_4b453cf8 PS1, Line 393: hwmInitSeq[65].val = 5; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f7b42f88_ecf31a11 PS1, Line 394: hwmInitSeq[66].val = 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8eb5be1e_88a15a34 PS1, Line 395: hwmInitSeq[67].val = 76; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1862118c_f4d66790 PS1, Line 396: hwmInitSeq[68].val = 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2dc55491_e9edf95d PS1, Line 397: hwmInitSeq[69].val = 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a5a69302_cf80f1f7 PS1, Line 398: hwmInitSeq[70].val = 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ba673ad4_8944bbc5 PS1, Line 399: hwmInitSeq[71].val = 2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cfd4c085_13846cae PS1, Line 400: hwmInitSeq[72].addr = 113; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/83981d84_b4b97687 PS1, Line 401: hwmInitSeq[72].val = 3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/afba7005_67ae8088 PS1, Line 402: hwmInitSeq[73].addr = 395; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/47c01e64_c5c85e6b PS1, Line 403: hwmInitSeq[74].addr = 396; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/24b859c4_71601735 PS1, Line 404: hwmInitSeq[73].val = 3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/65b98e22_038a5b0a PS1, Line 405: hwmInitSeq[74].val = 3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8b87710c_d749d05f PS1, Line 407: for (int i = 0; i < 75; ++i) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1860580e_2c9d82e7 PS1, Line 407: for (int i = 0; i < 75; ++i) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/42234317_b778cda7 PS1, Line 408: ec_write(1, hwmInitSeq[i].addr, hwmInitSeq[i].val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2675cbae_5125efce PS1, Line 408: ec_write(1, hwmInitSeq[i].addr, hwmInitSeq[i].val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a65e0404_55513e7a PS1, Line 409: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b51a28a1_4a8fdb16 PS1, Line 417: u16 port; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0764209d_65da335e PS1, Line 418: u8 mask; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/84ca654c_b7e0bd7c PS1, Line 419: u8 val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/29bd870f_7354b22c PS1, Line 424: static const struct sio_init init_table[] = { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/514d44ff_4377acfa PS1, Line 425: { 0x2E, 0x0FF, 0x55 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1fa0156d_bcba5646 PS1, Line 425: { 0x2E, 0x0FF, 0x55 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6955be46_d58d57ac PS1, Line 426: { 0x2E, 0x0FF, 7 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4cf6afb4_70668ee6 PS1, Line 426: { 0x2E, 0x0FF, 7 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/81636fc7_c5b7869a PS1, Line 427: { 0x2F, 0x0FF, 0x3F }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a9af3891_6407c676 PS1, Line 427: { 0x2F, 0x0FF, 0x3F }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID 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checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dda3bfb0_bb4a9c13 PS1, Line 467: { 0x2F, 0x0FF, 0x40 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d738d775_9ae4b193 PS1, Line 467: { 0x2F, 0x0FF, 0x40 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a4f6d2a8_bd67ee1a PS1, Line 468: { 0x2E, 0x0FF, 0x73 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/794d5517_04e9d29c PS1, Line 468: { 0x2E, 0x0FF, 0x73 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3be36ceb_0163d250 PS1, Line 469: { 0x2F, 0x0FF, 0x0A }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b41dcb40_9428debc PS1, Line 469: { 0x2F, 0x0FF, 0x0A }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fa991f04_8ba489bc PS1, Line 470: { 0x0A40, 0x0FF, 1 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/82fe56d6_335182c7 PS1, Line 470: { 0x0A40, 0x0FF, 1 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6c763030_2c71bb1b PS1, Line 471: { 0x0A41, 0x0FF, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6f6f54c8_9649400e PS1, Line 471: { 0x0A41, 0x0FF, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6194af63_3284b60a PS1, Line 472: { 0x0A45, 0x0FF, 0x18 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5fab9071_39f9243b PS1, Line 472: { 0x0A45, 0x0FF, 0x18 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9d8fa0a9_3691c96b PS1, Line 473: { 0x0A75, 0x0FF, 1 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/292fff0a_6102e692 PS1, Line 473: { 0x0A75, 0x0FF, 1 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dd2b9f45_80f5356c PS1, Line 474: { 0x0A65, 0x0FF, 0x0F }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cd966984_0c5007f5 PS1, Line 474: { 0x0A65, 0x0FF, 0x0F }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7b143c9d_b1d4cfea PS1, Line 475: { 0x2E, 0x0FF, 0x0AA }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/82819264_6aa0cc38 PS1, Line 475: { 0x2E, 0x0FF, 0x0AA }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f5a331ad_5ec54688 PS1, Line 476: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c487136d_7a722fec PS1, Line 478: for (int i = 0; i < ARRAY_SIZE(init_table); ++i) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2ab3e155_530038fa PS1, Line 479: if (init_table[i].mask == 0xff) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/29a36b3a_f5522e35 PS1, Line 479: if (init_table[i].mask == 0xff) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/04d2fd3c_8c2d9ee2 PS1, Line 479: if (init_table[i].mask == 0xff) { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6c2f2b01_3394f424 PS1, Line 480: outb(init_table[i].val, init_table[i].port); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/28ad3812_17451d58 PS1, Line 480: outb(init_table[i].val, init_table[i].port); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/792817c4_0f1314e9 PS1, Line 481: } else { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4048b102_e835052c PS1, Line 481: } else { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a152cf42_e53594af PS1, Line 481: } else { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/238e0e7e_18bb9f1c PS1, Line 482: u8 prev = inb(init_table[i].port); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5082d1dc_9bdd9b99 PS1, Line 482: u8 prev = inb(init_table[i].port); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/788126a3_4df515e0 PS1, Line 483: outb(prev & init_table[i].mask | init_table[i].val, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e8d5ed70_9933dfbd PS1, Line 483: outb(prev & init_table[i].mask | init_table[i].val, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/206682f9_838f8e3c PS1, Line 484: init_table[i].port); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/557bfea8_1b68b9bc PS1, Line 484: init_table[i].port); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b0f0eb2e_2a34055b PS1, Line 485: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c335d960_e772a46d PS1, Line 485: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/645a4b70_fc82ee73 PS1, Line 486: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a4347a46_d5c4911b PS1, Line 492: u8 ecmsg = inb(0xA01u); // Clear EC-to-Host mailbox please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dea21acb_ac6089d4 PS1, Line 493: outb(ecmsg, 0xA01u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9020e714_90ecf40f PS1, Line 495: outb(0, 0xA02u); // Set EC address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/06670463_ab3ccf46 PS1, Line 496: outb(0x80u, 0xA03u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7491bf78_64c2fc38 PS1, Line 498: outb(flags, 0xA04u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/80ebc210_8bcd7c72 PS1, Line 499: outb(1u, 0xA05u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6be8c5cb_db5b399a PS1, Line 501: outb(4u, 0xA02u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1df1beaf_8008b3b9 PS1, Line 503: if ( (flags & 1) != 0 ) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a26503fe_b712b315 PS1, Line 503: if ( (flags & 1) != 0 ) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ef66efce_29bd15d0 PS1, Line 503: if ( (flags & 1) != 0 ) space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b2e31b0f_7b8c0fee PS1, Line 504: outb(*val, 0xA04u); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c9739db4_83df51a4 PS1, Line 504: outb(*val, 0xA04u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fa2653c5_aeab34b3 PS1, Line 505: outb(addr & 0xff, 0xA06u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e7f1c5cf_2701423d PS1, Line 506: outb((addr >> 8) & 0xff, 0xA07u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ef69f851_3912d7aa PS1, Line 509: outb(1u, 0xA00u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/866ed7ba_939728c3 PS1, Line 510: int timeout = 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a614ee45_eeda613c PS1, Line 511: do please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3a7c83a3_69e1c85c PS1, Line 512: ++timeout; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f08f0857_b56dd0b7 PS1, Line 512: ++timeout; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b51cda2a_80b28b64 PS1, Line 513: while ( (inb(0xA01u) & 1) == 0 && timeout < 0xFFF ); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9b1555d7_210df44b PS1, Line 513: while ( (inb(0xA01u) & 1) == 0 && timeout < 0xFFF ); space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8d9f514c_6e98d77c PS1, Line 513: while ( (inb(0xA01u) & 1) == 0 && timeout < 0xFFF ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4f7c6f76_1db483da PS1, Line 515: outb(0x31u, 0xA08u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/104466a0_e086dad1 PS1, Line 516: outb(0xC0u, 0xA00u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bd3b9dee_ce2ce66e PS1, Line 518: if ( (flags & 1) == 0 ) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/012a7aa9_e9b4cfe8 PS1, Line 518: if ( (flags & 1) == 0 ) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/daeb5441_415dbb94 PS1, Line 518: if ( (flags & 1) == 0 ) space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3538a07b_f175ad35 PS1, Line 519: *val = inb(0xA04u); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e6ac13de_1e86632a PS1, Line 519: *val = inb(0xA04u); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3fb9f61e_b734ff00 PS1, Line 521: return 0; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/257ae469_effad1eb PS1, Line 525: u16 addr; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/03c3bada_0036aa18 PS1, Line 526: u8 val; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9a26a3a1_404f2f2c PS1, Line 527: u8 pad; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f7e71c68_dc472b0e PS1, Line 532: static const struct emi_init init_table1[] = { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/de0cb157_c7ea9b2c PS1, Line 533: { 0x8CC, 0x11, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/89cb0ebb_760ebd0e PS1, Line 533: { 0x8CC, 0x11, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3f9d56d6_3f3178c6 PS1, Line 534: { 0x8D0, 0x11, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a672632c_ed3dbc8f PS1, Line 534: { 0x8D0, 0x11, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4ba8c54e_51462949 PS1, Line 535: { 0x88C, 0x10, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f1559bdf_1a6e355c PS1, Line 535: { 0x88C, 0x10, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/91f38bbb_58a64349 PS1, Line 536: { 0x890, 0x10, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d2f28c7b_878c9f54 PS1, Line 536: { 0x890, 0x10, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0f0593af_e56bf073 PS1, Line 537: { 0x894, 0x10, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/722e2a1d_4fced1e5 PS1, Line 537: { 0x894, 0x10, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/39c94e23_f160b4f8 PS1, Line 538: { 0x898, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/268397b1_3ca2f813 PS1, Line 538: { 0x898, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/41da1cb5_2b0c42fc PS1, Line 539: { 0x89C, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cb05c9f5_06340fbc PS1, Line 539: { 0x89C, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6beeba9f_3f9f957e PS1, Line 540: { 0x8A0, 0x10, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/60b8345c_47c239b6 PS1, Line 540: { 0x8A0, 0x10, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/92c00a87_a9049a4f PS1, Line 541: { 0x8A4, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6d3cd097_d319d6a2 PS1, Line 541: { 0x8A4, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/703a846e_744e1a50 PS1, Line 542: { 0x8A8, 0x10, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/50c51b02_b43c57a8 PS1, Line 542: { 0x8A8, 0x10, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/52670886_6d379f5b PS1, Line 543: { 0x820, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2f745300_e0015b50 PS1, Line 543: { 0x820, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5421ccbb_73d37209 PS1, Line 544: { 0x824, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/defc0f74_7947c8b3 PS1, Line 544: { 0x824, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3ca66605_9fe1718a PS1, Line 545: { 0x878, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f06c7e9a_f4d1bbaf PS1, Line 545: { 0x878, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7f249f29_8eeba88c PS1, Line 546: { 0x880, 0x12, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4f4bcc26_7a5e0dfc PS1, Line 546: { 0x880, 0x12, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID 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ARRAY_SIZE(init_table1); ++i) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/40c54e50_e686ae22 PS1, Line 559: for (int i = 0; i < ARRAY_SIZE(init_table1); ++i) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7f6c0098_c95dbeeb PS1, Line 560: emi_data_rw(init_table1[i].addr, &init_table1[i].val, 5); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f25494b5_7df3211c PS1, Line 560: emi_data_rw(init_table1[i].addr, &init_table1[i].val, 5); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d6838271_010e6fa7 PS1, Line 561: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/0f5b2717_21020ca7 PS1, Line 563: static const struct emi_init init_table2[] = { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/75ea02e4_c0787a75 PS1, Line 564: { 5, 0x33, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3f9a1ada_92605302 PS1, Line 564: { 5, 0x33, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1e95565c_a5bbad27 PS1, Line 565: { 0x18, 0x2F, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f1c2f5d0_b688ad74 PS1, Line 565: { 0x18, 0x2F, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/038907f6_cc4e9822 PS1, Line 566: { 0x19, 0x2F, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2d98bc6f_317f68b5 PS1, Line 566: { 0x19, 0x2F, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/77a85a94_009f40bd PS1, Line 567: { 0x1A, 0x2F, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID 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}, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/165fa580_5c7aabec PS1, Line 572: { 0x8B, 0x60, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c199d6eb_f3b7294e PS1, Line 572: { 0x8B, 0x60, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c8c3c417_45bee358 PS1, Line 573: { 0x90, 0x5E, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ff12143f_a402ccc5 PS1, Line 573: { 0x90, 0x5E, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID 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0x0A4, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/248859cb_4191529b PS1, Line 578: { 0x98, 0x0A4, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/de431491_8d81d0bd PS1, Line 579: { 0x9B, 0x0A4, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a42b4a9c_0ebc6dd5 PS1, Line 579: { 0x9B, 0x0A4, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c761ec07_f29d31cc PS1, Line 580: { 0x0A0, 0x0A, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID 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jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/150f48ce_c5499586 PS1, Line 587: { 0x0B7, 8, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/878854de_d8777d7e PS1, Line 587: { 0x0B7, 8, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1d43606d_6f09b84b PS1, Line 588: { 0x0EA, 0x64, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e488693a_93e58d72 PS1, Line 588: { 0x0EA, 0x64, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): 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0, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/27443b96_cf16fdb3 PS1, Line 591: { 0x0F9, 0, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8fc2ba4b_03d36e73 PS1, Line 592: { 0x0F0, 0x30, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/297eaca7_dc9de749 PS1, Line 592: { 0x0F0, 0x30, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/36b00bd6_ca7ccb10 PS1, Line 593: { 0x0FD, 1, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/156162a5_a2a87170 PS1, Line 593: { 0x0FD, 1, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7b46be2c_7236555e PS1, Line 594: { 0x1A1, 0, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/67b3785b_eaa5da1e PS1, Line 594: { 0x1A1, 0, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/eb5a7713_e9be78df PS1, Line 595: { 0x1A2, 0, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ae80b28a_8a0c9add PS1, Line 595: { 0x1A2, 0, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7e4ca08e_c3db492d PS1, Line 596: { 0x1B1, 8, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b82d62c5_9ac4d69f PS1, Line 596: { 0x1B1, 8, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1274a55f_cb9a2906 PS1, Line 597: { 0x1BE, 0x90, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b61800cb_b638d7bd PS1, Line 597: { 0x1BE, 0x90, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9fac5c07_8f599914 PS1, Line 598: { 0x280, 0x24, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3f0ab41d_b2799446 PS1, Line 598: { 0x280, 0x24, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3866364c_ad0df4e9 PS1, Line 599: { 0x281, 0x13, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b6837a79_960d9a5d PS1, Line 599: { 0x281, 0x13, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2f9a9cf9_f17c1ec7 PS1, Line 600: { 0x282, 3, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/435bb6c6_ed3506e4 PS1, Line 600: { 0x282, 3, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/41c55f3d_cc0f5daa PS1, Line 601: { 0x283, 0x0A, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/88d4deb7_cf20de1d PS1, Line 601: { 0x283, 0x0A, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1c761bd8_94551d3c PS1, Line 602: { 0x284, 0x80, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6775de3b_b1b01428 PS1, Line 602: { 0x284, 0x80, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/60e1fe42_199edd1d PS1, Line 603: { 0x285, 3, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b4dee305_016e17f1 PS1, Line 603: { 0x285, 3, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1e2c570b_bb07d595 PS1, Line 604: { 0x288, 0x80, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/10c2ff0d_c6c243d3 PS1, Line 604: { 0x288, 0x80, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/daa81fbe_286b18ad PS1, Line 605: { 0x289, 0x0C, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/14dc7302_0c0e9f46 PS1, Line 605: { 0x289, 0x0C, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/81765d0d_224498ef PS1, Line 606: { 0x28A, 3, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9e6ff014_14287af9 PS1, Line 606: { 0x28A, 3, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/548a7bdc_069c86fa PS1, Line 607: { 0x28B, 0x0A, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4476a302_a9da66bf PS1, Line 607: { 0x28B, 0x0A, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/4adf5732_8524adc6 PS1, Line 608: { 0x28C, 0x80, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/bbcaaf1e_90939460 PS1, Line 608: { 0x28C, 0x80, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6f4565fc_ee7d7276 PS1, Line 609: { 0x28D, 3, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/193ff0e6_dd597a57 PS1, Line 609: { 0x28D, 3, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/cfe6c880_0ead9b2b PS1, Line 610: { 0x40, 1, 0 }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a545ac91_21428480 PS1, Line 610: { 0x40, 1, 0 }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/47cc048b_1968ee81 PS1, Line 611: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e9948ad3_bff2cbc6 PS1, Line 613: for (int i = 0; i < ARRAY_SIZE(init_table2); ++i) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d67a2be8_5d25f4c0 PS1, Line 613: for (int i = 0; i < ARRAY_SIZE(init_table2); ++i) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3f91c061_c8c7faff PS1, Line 614: emi_data_rw(init_table2[i].addr, &init_table2[i].val, 3); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c63e70c1_7509e48f PS1, Line 614: emi_data_rw(init_table2[i].addr, &init_table2[i].val, 3); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e1bf32c3_27dbecad PS1, Line 615: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/b9f9e757_98c6c5f0 PS1, Line 618: static void do_bios_init() Bad function definition - void do_bios_init() should probably be void do_bios_init(void) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7481df66_6ad73f59 PS1, Line 621: pci_write16(LPC_IO_DEC, 0x0000); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/31023cb8_e171a7f0 PS1, Line 622: pci_write32(LPC_GEN1_DEC, 0x007c0a01); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/20c26e95_8e991393 PS1, Line 623: pci_write32(LPC_GEN2_DEC, 0x007c0901); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/15864acf_4c42a05e PS1, Line 624: pci_write32(LPC_GEN3_DEC, 0x003c07e1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/94aa76bd_536372ef PS1, Line 625: pci_write32(LPC_GEN4_DEC, 0x001c0901); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3bfc6334_6992ecbd PS1, Line 628: printk(BIOS_DEBUG, "LPC_IO_DEC : %04x\n", pci_read16(LPC_IO_DEC)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c9214633_c5384a25 PS1, Line 629: printk(BIOS_DEBUG, "LPC_GEN1_DEC: %08x\n", pci_read32(LPC_GEN1_DEC)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e5ac7baf_780a953a PS1, Line 630: printk(BIOS_DEBUG, "LPC_GEN2_DEC: %08x\n", pci_read32(LPC_GEN2_DEC)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d55fc01c_2b869fee PS1, Line 631: printk(BIOS_DEBUG, "LPC_GEN3_DEC: %08x\n", pci_read32(LPC_GEN3_DEC)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d042e38d_8f0f0499 PS1, Line 632: printk(BIOS_DEBUG, "LPC_GEN4_DEC: %08x\n", pci_read32(LPC_GEN4_DEC)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/63e3be56_fd6c4303 PS1, Line 633: printk(BIOS_DEBUG, "\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8641e4a4_18ffbb57 PS1, Line 636: sio_init(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3bf072ff_df627351 PS1, Line 637: printk(BIOS_DEBUG, "SIO init done!\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c6bc9b05_2b0a8281 PS1, Line 638: emi_init(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/dfc65ae7_a6f734f9 PS1, Line 639: printk(BIOS_DEBUG, "EMI init done!\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/57b85857_3fddf8f3 PS1, Line 644: do_bios_init(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/84a9f34a_a687d66f PS1, Line 647: outb(0x55, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e6d78172_acac1d58 PS1, Line 648: smsc_write8(GLO_LDN_SELECT, 0x0c); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/355b0d98_8ff421f6 PS1, Line 649: emi_iobase = smsc_read16(0x64 + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/392c6467_c32e95c4 PS1, Line 650: runtime_iobase = smsc_read16(0x70 + 2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1c73a6d2_23596d2c PS1, Line 653: smsc_write16(0x68, 0x8707); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f5891c2a_a743887b PS1, Line 654: smsc_write16(0x68 + 2, CONFIG_TTYS0_BASE); // Serial Port I/O address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7693326f_c1fdaa80 PS1, Line 655: smsc_write8(GLO_LDN_SELECT, 0x07); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5bce8b0d_a53734d4 PS1, Line 656: smsc_write8(GLO_LDN_ACTIVE, 0x01); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/7bbc80d0_b75d459e PS1, Line 657: smsc_write8(UART_CONFIG_SELECT, 0x02); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/59c56453_4eac56b8 PS1, Line 659: outb(0xaa, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/a29fb581_2e1d540e PS1, Line 662: outb(runtime_iobase + 0x25, 3); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/621039d1_6111ffa6 PS1, Line 664: ec_initialize(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1c162f29_435a87e4 PS1, Line 666: hwm_init(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5f054c22_ea5929bf PS1, Line 669: outb(0x55, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1d6a98ab_ffa6c425 PS1, Line 670: for (struct smsc_ldn *ldn = ALL_LDNS; ldn->name != NULL; ++ldn) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fb1eb98e_616efbce PS1, Line 671: printk(BIOS_DEBUG, "Registers for %s (LDN: %02x)\n", ldn->name, ldn->ldn); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1df8094d_836831be PS1, Line 671: printk(BIOS_DEBUG, "Registers for %s (LDN: %02x)\n", ldn->name, ldn->ldn); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1d7e379f_7af21b79 PS1, Line 672: smsc_write8(GLO_LDN_SELECT, ldn->ldn); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f086cf0e_9eea8891 PS1, Line 672: smsc_write8(GLO_LDN_SELECT, ldn->ldn); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/50284c9c_2ebe41c2 PS1, Line 673: for (struct smsc_reg *reg = ldn->regs; reg->name != NULL; ++reg) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/01d1b997_a2bdf41d PS1, Line 673: for (struct smsc_reg *reg = ldn->regs; reg->name != NULL; ++reg) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5fb8fe16_e397ea7b PS1, Line 673: for (struct smsc_reg *reg = ldn->regs; reg->name != NULL; ++reg) { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/eaec2df4_3d284622 PS1, Line 674: switch (reg->width) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3b111f19_bbbdf132 PS1, Line 674: switch (reg->width) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/385d8d73_62d6801e PS1, Line 675: case WIDTH8: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e31ec490_d86d4474 PS1, Line 675: case WIDTH8: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e5351b7b_dd993de2 PS1, Line 676: printk(BIOS_DEBUG, " %s: %02x\n", reg->name, smsc_read8(reg->offset)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c96a79f9_932192b7 PS1, Line 676: printk(BIOS_DEBUG, " %s: %02x\n", reg->name, smsc_read8(reg->offset)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2f195b05_49e6f49f PS1, Line 677: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8d3ce011_f636b539 PS1, Line 677: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/15eed5a1_6828b007 PS1, Line 678: case WIDTH16: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/61329903_ffc19dfa PS1, Line 678: case WIDTH16: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9589975c_b87f1fa0 PS1, Line 679: printk(BIOS_DEBUG, " %s: %04x\n", reg->name, smsc_read16(reg->offset)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/8955a11c_22eaa92c PS1, Line 679: printk(BIOS_DEBUG, " %s: %04x\n", reg->name, smsc_read16(reg->offset)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1c73747e_9ba552d3 PS1, Line 680: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ceb372e0_55d6f66b PS1, Line 680: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3b959152_571f8b61 PS1, Line 681: case WIDTH32: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9e12cb33_b04b116c PS1, Line 681: case WIDTH32: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/646ac15a_f3c91043 PS1, Line 682: printk(BIOS_DEBUG, " %s: %08x\n", reg->name, smsc_read32(reg->offset)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/55573efe_ba9aaf66 PS1, Line 682: printk(BIOS_DEBUG, " %s: %08x\n", reg->name, smsc_read32(reg->offset)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/1cc9439c_b3bf0e72 PS1, Line 683: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/092fde6e_16628f92 PS1, Line 683: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ae6616ca_9e38bdb8 PS1, Line 684: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3d717d66_a445a85a PS1, Line 684: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/c42fb836_b16d70a5 PS1, Line 685: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/209880e7_e8452e5b PS1, Line 685: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/31d884e7_f8dc9df3 PS1, Line 686: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/65c029ab_68d6b7c0 PS1, Line 687: outb(0xaa, SMSC_INDEX); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/9567c00a_fa9c61c1 PS1, Line 694: u32 val = inl(emi_iobase + 4); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/62286341_71dbd044 PS1, Line 695: printk(BIOS_DEBUG, "%08x ", val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/fe0ce901_72f205ff PS1, Line 696: if ((i += 4) % 16 == 0) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/e1bb85a5_5860bce0 PS1, Line 697: printk(BIOS_DEBUG, "\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/3c9676e3_5de6486c PS1, Line 704: u32 val = inl(emi_iobase + 4); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/6b719357_0dc502f5 PS1, Line 705: printk(BIOS_DEBUG, "%08x ", val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d71b5ca6_2372fd72 PS1, Line 706: if ((i += 4) % 16 == 0) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/183f6e39_12092299 PS1, Line 707: printk(BIOS_DEBUG, "\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/f6300007_cec47f9e PS1, Line 714: outb(i, runtime_iobase + RUNTIME_GPIO_SELECT); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/98392534_be66ba7b PS1, Line 715: printk(BIOS_DEBUG, "%02x ", inb(runtime_iobase + RUNTIME_GPIO_READ)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/5d72fbd8_0560243a PS1, Line 716: if (++i % 16 == 0) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/acf9dbc8_eb969fca PS1, Line 717: printk(BIOS_DEBUG, "\n"); code indent should use tabs where possible File src/southbridge/intel/lynxpoint/early_pch.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/ddb6ad14_ae0fb290 PS1, Line 76: // return; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/d848b42a_51164866 PS1, Line 78: // config = dev->chip_info; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120793): https://review.coreboot.org/c/coreboot/+/55232/comment/2c8e9545_d8b0b15c PS1, Line 80: // return; please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/55232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:51:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/dell: Add OptiPlex 7020 SFF port
by Máté Kukri (Code Review) 04 Jun '21

04 Jun '21

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55232 ) Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ...................................................................... [WIP] mb/dell: Add OptiPlex 7020 SFF port Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- M Makefile.inc A src/mainboard/dell/optiplex_7020/Kconfig A src/mainboard/dell/optiplex_7020/Kconfig.name A src/mainboard/dell/optiplex_7020/Makefile.inc A src/mainboard/dell/optiplex_7020/acpi/ec.asl A src/mainboard/dell/optiplex_7020/acpi/platform.asl A src/mainboard/dell/optiplex_7020/acpi/superio.asl A src/mainboard/dell/optiplex_7020/board_info.txt A src/mainboard/dell/optiplex_7020/bootblock.c A src/mainboard/dell/optiplex_7020/cmos.default A src/mainboard/dell/optiplex_7020/cmos.layout A src/mainboard/dell/optiplex_7020/data.vbt A src/mainboard/dell/optiplex_7020/devicetree.cb A src/mainboard/dell/optiplex_7020/dsdt.asl A src/mainboard/dell/optiplex_7020/gma-mainboard.ads A src/mainboard/dell/optiplex_7020/gpio.c A src/mainboard/dell/optiplex_7020/hda_verb.c A src/mainboard/dell/optiplex_7020/io.h A src/mainboard/dell/optiplex_7020/mainboard.c A src/mainboard/dell/optiplex_7020/romstage.c A src/mainboard/dell/optiplex_7020/smscprog.c M src/northbridge/intel/haswell/raminit.c M src/southbridge/intel/lynxpoint/early_pch.c 23 files changed, 1,334 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/55232/1 diff --git a/Makefile.inc b/Makefile.inc index eb505e5..e1da353 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,7 +488,7 @@ endif ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) -CFLAGS_common += -Werror +# CFLAGS_common += -Werror endif ifneq ($(GDB_DEBUG),) CFLAGS_common += -Og diff --git a/src/mainboard/dell/optiplex_7020/Kconfig b/src/mainboard/dell/optiplex_7020/Kconfig new file mode 100644 index 0000000..57ca13b --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Kconfig @@ -0,0 +1,32 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_DELL_OPTIPLEX_7020 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config CBFS_SIZE + hex + default 0x100000 + +config MAINBOARD_DIR + string + default "dell/optiplex_7020" + +config MAINBOARD_PART_NUMBER + string + default "OptiPlex 7020" + +endif diff --git a/src/mainboard/dell/optiplex_7020/Kconfig.name b/src/mainboard/dell/optiplex_7020/Kconfig.name new file mode 100644 index 0000000..73600a6 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_OPTIPLEX_7020 + bool "OptiPlex 7020" diff --git a/src/mainboard/dell/optiplex_7020/Makefile.inc b/src/mainboard/dell/optiplex_7020/Makefile.inc new file mode 100644 index 0000000..d5e44fb --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += bootblock.c smscprog.c diff --git a/src/mainboard/dell/optiplex_7020/acpi/ec.asl b/src/mainboard/dell/optiplex_7020/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/ec.asl diff --git a/src/mainboard/dell/optiplex_7020/acpi/platform.asl b/src/mainboard/dell/optiplex_7020/acpi/platform.asl new file mode 100644 index 0000000..7615a32 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/platform.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + +} + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + + Name (_PRW, Package() { 8, 3}) + } +} diff --git a/src/mainboard/dell/optiplex_7020/acpi/superio.asl b/src/mainboard/dell/optiplex_7020/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/superio.asl diff --git a/src/mainboard/dell/optiplex_7020/board_info.txt b/src/mainboard/dell/optiplex_7020/board_info.txt new file mode 100644 index 0000000..38d931f --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-70… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/dell/optiplex_7020/bootblock.c b/src/mainboard/dell/optiplex_7020/bootblock.c new file mode 100644 index 0000000..02d2863 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void smsc5555_setup(void); + +void mainboard_config_superio(void) +{ + smsc5555_setup(); +} diff --git a/src/mainboard/dell/optiplex_7020/cmos.default b/src/mainboard/dell/optiplex_7020/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/dell/optiplex_7020/cmos.layout b/src/mainboard/dell/optiplex_7020/cmos.layout new file mode 100644 index 0000000..c9ba76c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/dell/optiplex_7020/data.vbt b/src/mainboard/dell/optiplex_7020/data.vbt new file mode 100644 index 0000000..1779f3b --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/data.vbt Binary files differ diff --git a/src/mainboard/dell/optiplex_7020/devicetree.cb b/src/mainboard/dell/optiplex_7020/devicetree.cb new file mode 100644 index 0000000..e057185 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/devicetree.cb @@ -0,0 +1,76 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + # This mainboard has VGA + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x1028 0x05a5 + end + + device pci 01.0 off end # PCIe graphics + + device pci 02.0 on # VGA controller + subsystemid 0x1028 0x05a5 + end + + device pci 03.0 on # Mini-HD audio + subsystemid 0x1028 0x05a5 + end + + chip southbridge/intel/lynxpoint + register "sata_port_map" = "0x33" + + register "gen1_dec" = "0x00000295" # Super I/O HWM + + device pci 14.0 on # xHCI controller + subsystemid 0x1028 0x05a5 + end + device pci 16.0 on # Management Engine interface 1 + subsystemid 0x1028 0x05a5 + end + device pci 16.1 off end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on # Management Engine KT + subsystemid 0x1028 0x05a5 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1028 0x05a4 + end + device pci 1a.0 on # EHCI controller #2 + subsystemid 0x1028 0x05a5 + end + device pci 1b.0 on # HD audio controller + subsystemid 0x1028 0x05a5 + end + device pci 1c.0 off end # PCIe port #1 + device pci 1c.1 off end # PCIe port #2 + device pci 1c.2 off end # PCIe port #3 + device pci 1c.3 off end # TODO: what's this? + device pci 1c.4 off end # TODO: what's this? + device pci 1c.5 off end # TODO: what's this? + device pci 1d.0 on # EHCI controller #1 + subsystemid 0x1028 0x05a5 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1028 0x05a5 + end + device pci 1f.2 on # SATA controller 1 + subsystemid 0x1028 0x05a5 + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x05a5 + end + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/optiplex_7020/dsdt.asl b/src/mainboard/dell/optiplex_7020/dsdt.asl new file mode 100644 index 0000000..8d4899a --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20181031 /* OEM Revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/dell/optiplex_7020/gma-mainboard.ads b/src/mainboard/dell/optiplex_7020/gma-mainboard.ads new file mode 100644 index 0000000..e7edb8e --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- TODO: Add DP ports to the list + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_7020/gpio.c b/src/mainboard/dell/optiplex_7020/gpio.c new file mode 100644 index 0000000..a281acf --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/gpio.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/optiplex_7020/hda_verb.c b/src/mainboard/dell/optiplex_7020/hda_verb.c new file mode 100644 index 0000000..467a888 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Realtek ALC3220 */ + 0x102805a5, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(1, 0x102805a5), + AZALIA_PIN_CFG(1, 0x12, 0x4008c000), + AZALIA_PIN_CFG(1, 0x13, 0x411111f0), + AZALIA_PIN_CFG(1, 0x14, 0x90170110), + AZALIA_PIN_CFG(1, 0x15, 0x0221401f), + AZALIA_PIN_CFG(1, 0x16, 0x411111f0), + AZALIA_PIN_CFG(1, 0x17, 0x411111f0), + AZALIA_PIN_CFG(1, 0x18, 0x01a13040), + AZALIA_PIN_CFG(1, 0x19, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1a, 0x02a19030), + AZALIA_PIN_CFG(1, 0x1b, 0x01014020), + AZALIA_PIN_CFG(1, 0x1d, 0x40400001), + AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_7020/io.h b/src/mainboard/dell/optiplex_7020/io.h new file mode 100644 index 0000000..4dcaed0 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/io.h @@ -0,0 +1,87 @@ +// +// PCI, Port, and other I/O access helpers +// + +#ifndef IO_H +#define IO_H + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +static inline uint8_t inb(uint16_t port) +{ + uint8_t r; + asm volatile ("inb %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline uint16_t inw(uint16_t port) +{ + uint16_t r; + asm volatile ("inw %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline uint32_t inl(uint16_t port) +{ + uint32_t r; + asm volatile ("inl %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline void outb(uint8_t val, uint16_t port) +{ + asm volatile ("outb %0, %1" : : "a"(val), "Nd"(port)); +} + +static inline void outw(uint16_t val, uint16_t port) +{ + asm volatile ("outw %0, %1" : : "a"(val), "Nd"(port)); +} + +static inline void outl(uint32_t val, uint16_t port) +{ + asm volatile ("outl %0, %1" : : "a"(val), "Nd"(port)); +} + +#define PCI_ADDR(bus, dev, fun, offs) \ + (bus << 16 | dev << 11 | fun << 8 | offs) + +static inline uint32_t pci_read32(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inl(0xcfc); +} + +static inline uint16_t pci_read16(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inw(0xcfc + (addr & 2)); +} + +static inline uint8_t pci_read8(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inb(0xcfc + (addr & 3)); +} + +static inline void pci_write32(uint32_t addr, uint32_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outl(val, 0xcfc); +} + +static inline void pci_write16(uint32_t addr, uint16_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outw(val, 0xcfc + (addr & 2)); +} + +static inline void pci_write8(uint32_t addr, uint8_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outb(val, 0xcfc + (addr & 3)); +} + +#endif diff --git a/src/mainboard/dell/optiplex_7020/mainboard.c b/src/mainboard/dell/optiplex_7020/mainboard.c new file mode 100644 index 0000000..f0dbc3f --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/optiplex_7020/romstage.c b/src/mainboard/dell/optiplex_7020/romstage.c new file mode 100644 index 0000000..540a6a1 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/romstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, + { 1, 0 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, +}; diff --git a/src/mainboard/dell/optiplex_7020/smscprog.c b/src/mainboard/dell/optiplex_7020/smscprog.c new file mode 100644 index 0000000..8527a3c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/smscprog.c @@ -0,0 +1,720 @@ +#include <console/console.h> +#include "io.h" + +// LPC registers +#define LPC_IO_DEC PCI_ADDR(0, 0x1f, 0, 0x80) +#define LPC_GEN1_DEC PCI_ADDR(0, 0x1f, 0, 0x84) +#define LPC_GEN2_DEC PCI_ADDR(0, 0x1f, 0, 0x88) +#define LPC_GEN3_DEC PCI_ADDR(0, 0x1f, 0, 0x8c) +#define LPC_GEN4_DEC PCI_ADDR(0, 0x1f, 0, 0x90) + +// I/O ports +#define SMSC_INDEX 0x2e +#define SMSC_DATA 0x2f + +// Global registers +#define GLO_LDN_SELECT 0x07 +#define GLO_DEVICE_ID 0x20 +#define GLO_DEVICE_REV 0x21 +#define GLO_DEVICE_MODE 0x24 + +// Activate the current LDN +#define GLO_LDN_ACTIVE 0x30 + +// UART registers +#define UART_CONFIG_SELECT 0xf0 + +// Runtime regsiters +#define RUNTIME_GPIO_SELECT 0x28 +#define RUNTIME_GPIO_READ 0x29 + +// +// Super I/O access +// + +static u8 smsc_read8(u8 offset) +{ + outb(offset, SMSC_INDEX); + return inb(SMSC_DATA); +} + +static u16 smsc_read16(u8 offset) +{ + u16 val = 0; + val |= smsc_read8(offset); + val |= smsc_read8(offset + 1) << 8; + return val; +} + +static u32 smsc_read32(u8 offset) +{ + u32 val = 0; + val |= smsc_read8(offset); + val |= smsc_read8(offset + 1) << 8; + val |= smsc_read8(offset + 2) << 16; + val |= smsc_read8(offset + 3) << 24; + return val; +} + +static void smsc_write8(u8 offset, u8 value) +{ + outb(offset, SMSC_INDEX); + outb(value, SMSC_DATA); +} + +static void smsc_write16(u8 offset, u16 value) +{ + smsc_write8(offset, value & 0xff); + smsc_write8(offset + 1, (value >> 8) & 0xff); +} + +static void smsc_write32(u8 offset, u32 value) +{ + smsc_write8(offset, value & 0xff); + smsc_write8(offset + 1, (value >> 8) & 0xff); + smsc_write8(offset + 2, (value >> 16) & 0xff); + smsc_write8(offset + 3, (value >> 24) & 0xff); +} + +// +// Super I/O registers +// + +enum smsc_width { + WIDTH8, + WIDTH16, + WIDTH32 +}; + +struct smsc_reg { + enum smsc_width width; + u8 offset; + const char *name; +}; + +struct smsc_ldn { + u8 ldn; + const char *name; + struct smsc_reg *regs; +}; + +static const struct smsc_ldn ALL_LDNS[] = { + { + .ldn = 0x3f, // NOTE: Selecting it is not necessary + .name = "Global Configuration ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x07, "Logical Device Number " }, + { WIDTH8, 0x20, "Device ID " }, + { WIDTH8, 0x21, "Device Revision " }, + { WIDTH8, 0x24, "Device Mode " }, + { 0, 0, 0 } + } + }, + { + .ldn = 0x0c, + .name = "LPC Interface ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x30, "Activate " }, + { WIDTH32, 0x60, "LPC Interface BAR " }, + { WIDTH32, 0x64, "EMI BAR " }, + { WIDTH32, 0x68, "UART1 BAR " }, + { WIDTH32, 0x6c, "UART2 BAR " }, + { WIDTH32, 0x70, "Runtime Registers BAR " }, + { WIDTH32, 0x74, "Undocumented BAR " }, + { WIDTH32, 0x78, "8042 BAR " }, + { WIDTH32, 0x7c, "Floppy Disk Controller BAR" }, + { WIDTH32, 0x80, "Parallel Port BAR " }, + { 0, 0, 0 } + } + }, + { + .ldn = 0x07, + .name = "UART1 ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x30, "Activate " }, + { WIDTH8, 0xf0, "Configuration Select " }, + { 0, 0, 0 } + } + }, + { 0, 0, 0 } +}; + + +// +// EMI access +// + +static u16 emi_iobase, runtime_iobase; + +static u8 emi_read8(u16 addr) +{ + outw(addr | 0x8000, emi_iobase + 2); + return inb(emi_iobase + 4); +} + +static u16 emi_read16(u16 addr) +{ + outw(addr | 0x8001, emi_iobase + 2); + return inw(emi_iobase + 4); +} + +static u32 emi_read32(u16 addr) +{ + outw(addr | 0x8002, emi_iobase + 2); + return inl(emi_iobase + 4); +} + +void emi_write8(u16 addr, u8 val) +{ + outw(addr | 0x8000, emi_iobase + 2); + outb(val, emi_iobase + 4); +} + +void emi_write16(u16 addr, u16 val) +{ + outw(addr | 0x8001, emi_iobase + 2); + outw(val, emi_iobase + 4); +} + +void emi_write32(u16 addr, u32 val) +{ + outw(addr | 0x8002, emi_iobase + 2); + outl(val, emi_iobase + 4); +} + +// +// Communicate with the EC (via EMI) +// + +void ec_initialize(void) +{ + inb(emi_iobase + 1); // EC-to-Host Mailbox + u8 int_src = inb(emi_iobase + 8) & 0xF6; // Interrupt Source (Byte 0) + outb(emi_iobase + 8, int_src); // Clear all Interrupts but 2, clear EC_WR +} + +_Bool ec_mailbox_xchg(u8 val) +{ + u8 int_src; + + outb(val, emi_iobase); // Send value via Host-to-EC mailbox + + do { + int_src = inb(emi_iobase + 8) & 0x71; // 0x71 = 0b1110001 + } while ( !int_src ); + outb(int_src, emi_iobase + 8); + + // Check EC_WR bit + if ((int_src & 1) == 0) + return 0; + + // Check if we got the same value via EC-to-Host mailbox + return val == inb(emi_iobase + 1); +} + +void ec_write(u8 addr1, u16 addr2, u8 val) +{ + u8 int_src = inb(emi_iobase + 0xA); // Save interrupt mask + outb(emi_iobase + 0xA, 0); // Mask all interrupts + emi_write16(0, (2 * addr1) | 0x101); + emi_write32(4, val | (addr2 << 16)); + ec_mailbox_xchg(1); + outb(emi_iobase + 0xA, int_src); // Restore interrupt mask +} + +u8 ec_read(u8 addr1, u16 addr2) +{ + u8 val = 0; + u8 int_src = inb(emi_iobase + 0xA); // save interrupt mask + outb(emi_iobase + 0xA, 0); // mask all interrupts + emi_write16(0, 2 * (addr1 | 0x80)); + emi_write32(4, addr2 << 16); + if (ec_mailbox_xchg(1)) + val = emi_read8(4); + outb(emi_iobase + 0xA, int_src); // restore interrupt mask + return val; +} + +// +// HWM initialization +// + +typedef struct { + u16 addr; + u8 val; +} BulkComEnt; + +static char *strcpy(char *s1, const char *s2) +{ + char *r = s1; + while (*s2) + *s1++ = *s2++; + return r; +} + +static void hwm_init(void) +{ + printk(BIOS_DEBUG, "EC 0xcb: %02x\n", ec_read(1, 0xcb)); + printk(BIOS_DEBUG, "EC 0xb8: %02x\n", ec_read(1, 0xb8)); + + BulkComEnt hwmInitSeq[75]; + + hwmInitSeq[0].addr = 0x2FC; + hwmInitSeq[1].addr = 0x2FD; + hwmInitSeq[2].addr = 5; + hwmInitSeq[3].addr = 0x19; + hwmInitSeq[4].addr = 0x1A; + hwmInitSeq[5].addr = 0x8A; + hwmInitSeq[6].addr = 0x8B; + hwmInitSeq[7].addr = 0x8C; + hwmInitSeq[8].addr = 0xBA; + hwmInitSeq[9].addr = 0xD1; + hwmInitSeq[10].addr = 0xD6; + hwmInitSeq[11].addr = 219; + hwmInitSeq[13].addr = 73; + hwmInitSeq[14].addr = 122; + hwmInitSeq[15].addr = 123; + hwmInitSeq[16].addr = 124; + hwmInitSeq[17].addr = 128; + hwmInitSeq[18].addr = 129; + hwmInitSeq[12].addr = 72; + hwmInitSeq[19].addr = 130; + hwmInitSeq[20].addr = 131; + hwmInitSeq[21].addr = 132; + hwmInitSeq[0].val = -96; + hwmInitSeq[1].val = 50; + hwmInitSeq[2].val = 119; + hwmInitSeq[3].val = 47; + hwmInitSeq[4].val = 47; + hwmInitSeq[5].val = 51; + hwmInitSeq[6].val = 51; + hwmInitSeq[7].val = 51; + hwmInitSeq[8].val = 16; + hwmInitSeq[9].val = -1; + hwmInitSeq[10].val = -1; + hwmInitSeq[11].val = -1; + hwmInitSeq[12].val = 0; + hwmInitSeq[13].val = 0; + hwmInitSeq[14].val = 0; + hwmInitSeq[15].val = 0; + hwmInitSeq[16].val = 0; + hwmInitSeq[17].val = 0; + hwmInitSeq[18].val = 0; + hwmInitSeq[19].val = 0; + hwmInitSeq[20].val = -69; + hwmInitSeq[21].val = -80; + hwmInitSeq[22].addr = 417; + hwmInitSeq[22].val = -120; + hwmInitSeq[23].addr = 420; + hwmInitSeq[24].addr = 136; + hwmInitSeq[25].addr = 137; + hwmInitSeq[26].addr = 160; + hwmInitSeq[27].addr = 161; + hwmInitSeq[28].addr = 162; + hwmInitSeq[29].addr = 164; + hwmInitSeq[30].addr = 165; + hwmInitSeq[31].addr = 166; + hwmInitSeq[32].addr = 171; + hwmInitSeq[33].addr = 173; + hwmInitSeq[34].addr = 183; + hwmInitSeq[35].addr = 98; + hwmInitSeq[42].addr = 89; + hwmInitSeq[43].addr = 97; + hwmInitSeq[44].addr = 444; + hwmInitSeq[45].addr = 445; + hwmInitSeq[23].val = 0x80; + hwmInitSeq[24].val = 0; + hwmInitSeq[25].val = 0; + hwmInitSeq[26].val = 2; + hwmInitSeq[27].val = 2; + hwmInitSeq[28].val = 2; + hwmInitSeq[29].val = 4; + hwmInitSeq[30].val = 4; + hwmInitSeq[31].val = 4; + hwmInitSeq[32].val = 0; + hwmInitSeq[33].val = 63; + hwmInitSeq[34].val = 7; + strcpy(&hwmInitSeq[35].val, "Pc"); + strcpy(&hwmInitSeq[36].val, "Fd"); + strcpy(&hwmInitSeq[37].val, "Pe"); + strcpy(&hwmInitSeq[38].val, "Ff"); + strcpy(&hwmInitSeq[39].val, "Pg"); + strcpy(&hwmInitSeq[40].val, "FW"); + hwmInitSeq[41].val = -104; + hwmInitSeq[42].val = -104; + hwmInitSeq[43].val = 124; + hwmInitSeq[44].val = 0; + hwmInitSeq[45].val = 0; + hwmInitSeq[46].addr = 443; + hwmInitSeq[46].val = 0; + hwmInitSeq[47].addr = 133; + hwmInitSeq[48].addr = 134; + hwmInitSeq[49].addr = 135; + hwmInitSeq[50].addr = 144; + hwmInitSeq[51].addr = 145; + hwmInitSeq[52].addr = 149; + hwmInitSeq[53].addr = 150; + hwmInitSeq[54].addr = 151; + hwmInitSeq[55].addr = 155; + hwmInitSeq[56].addr = 174; + hwmInitSeq[54].val = 0; + hwmInitSeq[55].val = 0; + hwmInitSeq[63].val = 0; + hwmInitSeq[57].addr = 175; + hwmInitSeq[58].addr = 179; + hwmInitSeq[64].addr = 691; + hwmInitSeq[59].addr = 196; + hwmInitSeq[65].addr = 692; + hwmInitSeq[66].addr = 716; + hwmInitSeq[67].addr = 720; + hwmInitSeq[68].addr = 722; + hwmInitSeq[59].val = -1; + hwmInitSeq[60].val = -1; + hwmInitSeq[61].val = -1; + hwmInitSeq[69].addr = 731; + hwmInitSeq[70].addr = 111; + hwmInitSeq[60].addr = 197; + hwmInitSeq[71].addr = 112; + hwmInitSeq[47].val = -35; + hwmInitSeq[48].val = -35; + hwmInitSeq[49].val = 7; + hwmInitSeq[50].val = -126; + hwmInitSeq[51].val = 94; + hwmInitSeq[52].val = 93; + hwmInitSeq[53].val = -87; + hwmInitSeq[56].val = -122; + hwmInitSeq[57].val = -122; + hwmInitSeq[58].val = 103; + hwmInitSeq[61].addr = 201; + hwmInitSeq[62].addr = 64; + hwmInitSeq[62].val = 1; + hwmInitSeq[63].addr = 0x2FC; + hwmInitSeq[64].val = -102; + hwmInitSeq[65].val = 5; + hwmInitSeq[66].val = 1; + hwmInitSeq[67].val = 76; + hwmInitSeq[68].val = 1; + hwmInitSeq[69].val = 1; + hwmInitSeq[70].val = 1; + hwmInitSeq[71].val = 2; + hwmInitSeq[72].addr = 113; + hwmInitSeq[72].val = 3; + hwmInitSeq[73].addr = 395; + hwmInitSeq[74].addr = 396; + hwmInitSeq[73].val = 3; + hwmInitSeq[74].val = 3; + + for (int i = 0; i < 75; ++i) { + ec_write(1, hwmInitSeq[i].addr, hwmInitSeq[i].val); + } +} + +// +// Super I/O initialization sequence +// + +struct sio_init { + u16 port; + u8 mask; + u8 val; +}; + +static void sio_init(void) +{ + static const struct sio_init init_table[] = { + { 0x2E, 0x0FF, 0x55 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x3F }, + { 0x2E, 0x0FF, 0x24 }, + { 0x2F, 0x0FB, 4 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x64 }, + { 0x2F, 0x0FF, 0x0F }, + { 0x2E, 0x0FF, 0x65 }, + { 0x2F, 0x0FF, 0x80 }, + { 0x2E, 0x0FF, 0x66 }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 0x67 }, + { 0x2F, 0x0FF, 0x0A }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x79 }, + { 0x2F, 0x0FF, 0x81 }, + { 0x2E, 0x0FF, 0x7A }, + { 0x2F, 0x0FF, 0x60 }, + { 0x2E, 0x0FF, 0x7B }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 0x41 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x4C }, + { 0x2F, 0x0FF, 0x81 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x30 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x0F0 }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x70 }, + { 0x2F, 0x0FF, 0x3F }, + { 0x2E, 0x0FF, 0x71 }, + { 0x2F, 0x0FF, 0x8A }, + { 0x2E, 0x0FF, 0x72 }, + { 0x2F, 0x0FF, 0x40 }, + { 0x2E, 0x0FF, 0x73 }, + { 0x2F, 0x0FF, 0x0A }, + { 0x0A40, 0x0FF, 1 }, + { 0x0A41, 0x0FF, 0 }, + { 0x0A45, 0x0FF, 0x18 }, + { 0x0A75, 0x0FF, 1 }, + { 0x0A65, 0x0FF, 0x0F }, + { 0x2E, 0x0FF, 0x0AA }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table); ++i) { + if (init_table[i].mask == 0xff) { + outb(init_table[i].val, init_table[i].port); + } else { + u8 prev = inb(init_table[i].port); + outb(prev & init_table[i].mask | init_table[i].val, + init_table[i].port); + } + } +} + + +int emi_data_rw(u16 addr, u8 *val, u8 flags) +{ + u8 ecmsg = inb(0xA01u); // Clear EC-to-Host mailbox + outb(ecmsg, 0xA01u); + + outb(0, 0xA02u); // Set EC address + outb(0x80u, 0xA03u); + + outb(flags, 0xA04u); + outb(1u, 0xA05u); + + outb(4u, 0xA02u); + + if ( (flags & 1) != 0 ) + outb(*val, 0xA04u); + outb(addr & 0xff, 0xA06u); + outb((addr >> 8) & 0xff, 0xA07u); + + + outb(1u, 0xA00u); + int timeout = 0; + do + ++timeout; + while ( (inb(0xA01u) & 1) == 0 && timeout < 0xFFF ); + + outb(0x31u, 0xA08u); + outb(0xC0u, 0xA00u); + + if ( (flags & 1) == 0 ) + *val = inb(0xA04u); + + return 0; +} + +struct emi_init { + u16 addr; + u8 val; + u8 pad; +}; + +static void emi_init(void) +{ + static const struct emi_init init_table1[] = { + { 0x8CC, 0x11, 0 }, + { 0x8D0, 0x11, 0 }, + { 0x88C, 0x10, 0 }, + { 0x890, 0x10, 0 }, + { 0x894, 0x10, 0 }, + { 0x898, 0x12, 0 }, + { 0x89C, 0x12, 0 }, + { 0x8A0, 0x10, 0 }, + { 0x8A4, 0x12, 0 }, + { 0x8A8, 0x10, 0 }, + { 0x820, 0x12, 0 }, + { 0x824, 0x12, 0 }, + { 0x878, 0x12, 0 }, + { 0x880, 0x12, 0 }, + { 0x884, 0x12, 0 }, + { 0x8E0, 0x12, 0 }, + { 0x8E4, 0x12, 0 }, + { 0x83C, 0x10, 0 }, + { 0x840, 0x10, 0 }, + { 0x844, 0x10, 0 }, + { 0x848, 0x10, 0 }, + { 0x84C, 0x10, 0 }, + { 0x850, 0x10, 0 }, + { 0x814, 0x11, 0 }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table1); ++i) { + emi_data_rw(init_table1[i].addr, &init_table1[i].val, 5); + } + + static const struct emi_init init_table2[] = { + { 5, 0x33, 0 }, + { 0x18, 0x2F, 0 }, + { 0x19, 0x2F, 0 }, + { 0x1A, 0x2F, 0 }, + { 0x83, 0x0BB, 0 }, + { 0x85, 0x0D9, 0 }, + { 0x86, 0x2C, 0 }, + { 0x8A, 0x34, 0 }, + { 0x8B, 0x60, 0 }, + { 0x90, 0x5E, 0 }, + { 0x91, 0x5E, 0 }, + { 0x92, 0x86, 0 }, + { 0x96, 0x0A4, 0 }, + { 0x97, 0x0A4, 0 }, + { 0x98, 0x0A4, 0 }, + { 0x9B, 0x0A4, 0 }, + { 0x0A0, 0x0A, 0 }, + { 0x0A1, 0x0A, 0 }, + { 0x0AE, 0x7C, 0 }, + { 0x0AF, 0x7C, 0 }, + { 0x0B0, 0x9E, 0 }, + { 0x0B3, 0x7C, 0 }, + { 0x0B6, 8, 0 }, + { 0x0B7, 8, 0 }, + { 0x0EA, 0x64, 0 }, + { 0x0EF, 0x0FF, 0 }, + { 0x0F8, 0x15, 0 }, + { 0x0F9, 0, 0 }, + { 0x0F0, 0x30, 0 }, + { 0x0FD, 1, 0 }, + { 0x1A1, 0, 0 }, + { 0x1A2, 0, 0 }, + { 0x1B1, 8, 0 }, + { 0x1BE, 0x90, 0 }, + { 0x280, 0x24, 0 }, + { 0x281, 0x13, 0 }, + { 0x282, 3, 0 }, + { 0x283, 0x0A, 0 }, + { 0x284, 0x80, 0 }, + { 0x285, 3, 0 }, + { 0x288, 0x80, 0 }, + { 0x289, 0x0C, 0 }, + { 0x28A, 3, 0 }, + { 0x28B, 0x0A, 0 }, + { 0x28C, 0x80, 0 }, + { 0x28D, 3, 0 }, + { 0x40, 1, 0 }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table2); ++i) { + emi_data_rw(init_table2[i].addr, &init_table2[i].val, 3); + } +} + +static void do_bios_init() +{ + // Change LPC config + pci_write16(LPC_IO_DEC, 0x0000); + pci_write32(LPC_GEN1_DEC, 0x007c0a01); + pci_write32(LPC_GEN2_DEC, 0x007c0901); + pci_write32(LPC_GEN3_DEC, 0x003c07e1); + pci_write32(LPC_GEN4_DEC, 0x001c0901); + + // Dump LPC config + printk(BIOS_DEBUG, "LPC_IO_DEC : %04x\n", pci_read16(LPC_IO_DEC)); + printk(BIOS_DEBUG, "LPC_GEN1_DEC: %08x\n", pci_read32(LPC_GEN1_DEC)); + printk(BIOS_DEBUG, "LPC_GEN2_DEC: %08x\n", pci_read32(LPC_GEN2_DEC)); + printk(BIOS_DEBUG, "LPC_GEN3_DEC: %08x\n", pci_read32(LPC_GEN3_DEC)); + printk(BIOS_DEBUG, "LPC_GEN4_DEC: %08x\n", pci_read32(LPC_GEN4_DEC)); + printk(BIOS_DEBUG, "\n"); + + // Do Sio and EMI Initialization + sio_init(); + printk(BIOS_DEBUG, "SIO init done!\n"); + emi_init(); + printk(BIOS_DEBUG, "EMI init done!\n"); +} + +void smsc5555_setup(void) +{ + do_bios_init(); + + // Save BAR values + outb(0x55, SMSC_INDEX); + smsc_write8(GLO_LDN_SELECT, 0x0c); + emi_iobase = smsc_read16(0x64 + 2); + runtime_iobase = smsc_read16(0x70 + 2); + + // Configure serial port + smsc_write16(0x68, 0x8707); + smsc_write16(0x68 + 2, CONFIG_TTYS0_BASE); // Serial Port I/O address + smsc_write8(GLO_LDN_SELECT, 0x07); + smsc_write8(GLO_LDN_ACTIVE, 0x01); + smsc_write8(UART_CONFIG_SELECT, 0x02); + + outb(0xaa, SMSC_INDEX); + + // Change LED to always on + outb(runtime_iobase + 0x25, 3); + // Setup EMI module + ec_initialize(); + // Do HWM init + hwm_init(); + + // Dump registers + outb(0x55, SMSC_INDEX); + for (struct smsc_ldn *ldn = ALL_LDNS; ldn->name != NULL; ++ldn) { + printk(BIOS_DEBUG, "Registers for %s (LDN: %02x)\n", ldn->name, ldn->ldn); + smsc_write8(GLO_LDN_SELECT, ldn->ldn); + for (struct smsc_reg *reg = ldn->regs; reg->name != NULL; ++reg) { + switch (reg->width) { + case WIDTH8: + printk(BIOS_DEBUG, " %s: %02x\n", reg->name, smsc_read8(reg->offset)); + break; + case WIDTH16: + printk(BIOS_DEBUG, " %s: %04x\n", reg->name, smsc_read16(reg->offset)); + break; + case WIDTH32: + printk(BIOS_DEBUG, " %s: %08x\n", reg->name, smsc_read32(reg->offset)); + break; + } + } + } + outb(0xaa, SMSC_INDEX); + +/* + // Dump EC Bank 0 + printk(BIOS_DEBUG, "\nEMI RAM Bank 0:\n"); + outw(0x0003, emi_iobase + 2); + for (int i = 0; i < 8192;) { + u32 val = inl(emi_iobase + 4); + printk(BIOS_DEBUG, "%08x ", val); + if ((i += 4) % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } + + // Dump EC Bank 1o + printk(BIOS_DEBUG, "\nEMI RAM Bank 1:\n"); + outw(0x8003, emi_iobase + 2); + for (int i = 0; i < 8192;) { + u32 val = inl(emi_iobase + 4); + printk(BIOS_DEBUG, "%08x ", val); + if ((i += 4) % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } + + + // Dump GPIOs + printk(BIOS_DEBUG, "\nGPIO:\n"); + for (int i = 0; i < 64;) { + outb(i, runtime_iobase + RUNTIME_GPIO_SELECT); + printk(BIOS_DEBUG, "%02x ", inb(runtime_iobase + RUNTIME_GPIO_READ)); + if (++i % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } +*/ +} diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9660961..9ee1023 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -139,7 +139,9 @@ */ entry = cbfs_ro_map("mrc.bin", NULL); if (entry) { + printk(BIOS_DEBUG, "Just before MRC entry!\n"); int rv = entry(pei_data); + printk(BIOS_DEBUG, "MRC entry returned: %d!\n", rv); /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 03823ff..c93f968 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -56,8 +56,8 @@ void pch_enable_lpc(void) { - const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_lynxpoint_config *config = NULL; + // const struct device *dev = pcidev_on_root(0x1f, 0); + // const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); @@ -67,18 +67,22 @@ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); - /* Set up generic decode ranges */ - if (!dev) - return; - if (dev->chip_info) - config = dev->chip_info; - if (!config) - return; + // FIXME: this is a horible hack + // Decode EMI at 0xa00 + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0a01); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); + /* Set up generic decode ranges */ + // if (!dev) + // return; + // if (dev->chip_info) + // config = dev->chip_info; + // if (!config) + // return; + + // pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } void __weak mainboard_config_superio(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/55232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch: Drop P_LVLx support in FADT
by Patrick Rudolph (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55220 ) Change subject: soc/intel/broadwell/pch: Drop P_LVLx support in FADT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f71ef99396b56dbd960c507133c06a8eae55778 Gerrit-Change-Number: 55220 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:50:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Unbreak master
by Star Labs (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak. Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55231 ) Change subject: mb/starlabs/labtop: Unbreak master ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Gerrit-Change-Number: 55231 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:49:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Unbreak master
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Star Labs, Tim Wawrzynczak. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55231 ) Change subject: mb/starlabs/labtop: Unbreak master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Gerrit-Change-Number: 55231 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:47:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/starlabs/labtop: Unbreak master
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55231 ) Change subject: mb/starlabs/labtop: Unbreak master ...................................................................... mb/starlabs/labtop: Unbreak master Missed a few things in review: 1) smbios_mainboard_serial_number 2) SMBIOS_FEATURE_FLAGS_HOSTING_BOARD 3) SMBIOS_FEATURE_FLAGS_REPLACEABLE Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/starlabs/labtop/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/55231/1 diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 4fe4af3..b398d74 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -40,7 +40,7 @@ /* Override smbios_mainboard_features_flags */ u8 smbios_mainboard_feature_flags(void) { - return SMBIOS_FEATURE_FLAG_HOSTING_BOARD | SMBIOS_FEATURE_FLAG_REPLACEABLE; + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; } /* Override smbios_mainboard_location_in_chassis */ @@ -79,7 +79,7 @@ } /* Override smbios_chassis_asset_tag */ -const char *smbios_chassis_asset_tag(void) +const char *smbios_mainboard_serial_number(void) { return CONFIG_MAINBOARD_SERIAL_NUMBER; } -- To view, visit https://review.coreboot.org/c/coreboot/+/55231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379880b1165bb9da4117aa860dee111fba38a43f Gerrit-Change-Number: 55231 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/sm: Use device aliases
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55206 ) Change subject: mb/intel/sm: Use device aliases ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55206/comment/158c573a_64371934 PS4, Line 180: device ref pcie4_0 on end > ahh yes, I remember the reason, my bad. […] Thanks for catching this! -- To view, visit https://review.coreboot.org/c/coreboot/+/55206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Gerrit-Change-Number: 55206 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:38:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021