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Change subject: mb/intel/sm: Use device aliases
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55206/comment/d4c8213f_076a1155
PS4, Line 180: device ref pcie4_0 on end
> this is off in the original […]
ahh yes, I remember the reason, my bad. Thanks Tim
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Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/55127/comment/b8f22a13_bac4d9f5
PS7, Line 16: 1536
> suggestion: […]
Hi Tim, I am getting asl compilation error if I don't use this define as hardcoded value directly. This defines is used in a Field(). It seems that the asl compiler won't pre-calculate for the value. I look around other Field() in asl files, I only see direct value been used as argument.
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Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55015/comment/03ea2c61_fd6d08b0
PS3, Line 35: };
> Instead of using raw indexes into `VtdBaseAddress` below, can we add more values here?
Done
https://review.coreboot.org/c/coreboot/+/55015/comment/414aab3d_c397bb70
PS3, Line 235: 3
> with above comment, something like VTD_TBT0, etc.
Ack
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Change subject: acpi: rework BERT SSDT generation logic
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/acpi/acpi_bert.c:
https://review.coreboot.org/c/coreboot/+/55054/comment/78cb5645_f07e7276
PS1, Line 13: SOC_INTEL_CRASHLOG
> iirc an undefined Kconfig symbol evaluates as false, so this does work as expected even though it pr […]
Ack
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Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
......................................................................
soc/intel/alderlake: Correct TCSS XHCI Port status offset
The patch corrects TCSS XHCI Port status offset. The information is
captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619502).
BUG=None
TEST=Verified boot on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59
---
M src/soc/intel/alderlake/xhci.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/55230/1
diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c
index 9226336..c2a4654 100644
--- a/src/soc/intel/alderlake/xhci.c
+++ b/src/soc/intel/alderlake/xhci.c
@@ -15,7 +15,7 @@
#define PCH_XHCI_USB3_PORT_NUM 4
#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480
-#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540
+#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490
#define TCSS_XHCI_USB2_PORT_NUM 10
#define TCSS_XHCI_USB3_PORT_NUM 4
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Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55015
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
......................................................................
soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.
TEST=Verified boot on Brya
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Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
---
M src/soc/intel/alderlake/romstage/fsp_params.c
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Change subject: acpi: rename acpi_soc_fill_bert and add return value
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
PS1:
> adding an open comment so the patch won't be merged before Tim had a chance to verify that the patch […]
This patch train is verified.
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Change subject: cpu/x86: Default to PARALLEL_MP selected
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/55196/comment/8c40021a_b0c7f574
PS3, Line 6: PARALLEL_MP
It might be a good idea to guard it for single CPU systems: depends on MAX_CPUS != 1, or depends on SMP.
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Change subject: cpu/x86/lapic: Drop read/write_around aliases
......................................................................
Patch Set 2: Code-Review+2
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