coreboot-gerrit June 2021

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Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 ) Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/xhci.c: https://review.coreboot.org/c/coreboot/+/55230/comment/62e21096_cd7d3012 PS1, Line 18: 0x490 This doesn't seem right. The port status registers start at 0x480 offset from MBAR, and there are 10 USB2 ports on ADL-P. The registers are spaced 0x10 bytes apart, therefore `0x480 + 0x10 * 9 = 0x510`, meaning the USB2 PORTSC and PORTPMSC2 registers must occupy `0x480 - 0x510`, right? So the USB3 PORTSC registers would have to start after 0x510? The EDS is very confusing to me in this regard. Am I misunderstanding? -- To view, visit https://review.coreboot.org/c/coreboot/+/55230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Gerrit-Change-Number: 55230 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:10:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55225/comment/a2f3e829_8c1b8e63 PS1, Line 12: This would help to increase the code readability and in future : meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly > Me too! […] Thanks Furquan and Tim for your support as always. Coming to Tim's proposal, yes, its a valid request. I have started working with FSP team to see if we can club those meaning UPDs inside a structure -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:09:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/sm: Use device aliases
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55206 ) Change subject: mb/intel/sm: Use device aliases ...................................................................... Patch Set 5: (1 comment) File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55206/comment/d4c8213f_076a1155 PS4, Line 180: device ref pcie4_0 on end > this is off in the original […] ahh yes, I remember the reason, my bad. Thanks Tim -- To view, visit https://review.coreboot.org/c/coreboot/+/55206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Gerrit-Change-Number: 55206 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:07:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/b8f22a13_bac4d9f5 PS7, Line 16: 1536 > suggestion: […] Hi Tim, I am getting asl compilation error if I don't use this define as hardcoded value directly. This defines is used in a Field(). It seems that the asl compiler won't pre-calculate for the value. I look around other Field() in asl files, I only see direct value been used as argument. -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 17:04:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
by Sridhar Siricilla (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55015 ) Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55015/comment/03ea2c61_fd6d08b0 PS3, Line 35: }; > Instead of using raw indexes into `VtdBaseAddress` below, can we add more values here? Done https://review.coreboot.org/c/coreboot/+/55015/comment/414aab3d_c397bb70 PS3, Line 235: 3 > with above comment, something like VTD_TBT0, etc. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Gerrit-Change-Number: 55015 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 16:57:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: rework BERT SSDT generation logic
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Francois Toguo Fotso, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55054 ) Change subject: acpi: rework BERT SSDT generation logic ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/55054/comment/78cb5645_f07e7276 PS1, Line 13: SOC_INTEL_CRASHLOG > iirc an undefined Kconfig symbol evaluates as false, so this does work as expected even though it pr […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea Gerrit-Change-Number: 55054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 16:55:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset
by Sridhar Siricilla (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55230 ) Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset ...................................................................... soc/intel/alderlake: Correct TCSS XHCI Port status offset The patch corrects TCSS XHCI Port status offset. The information is captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619502). BUG=None TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 --- M src/soc/intel/alderlake/xhci.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/55230/1 diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c index 9226336..c2a4654 100644 --- a/src/soc/intel/alderlake/xhci.c +++ b/src/soc/intel/alderlake/xhci.c @@ -15,7 +15,7 @@ #define PCH_XHCI_USB3_PORT_NUM 4 #define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480 -#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540 +#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490 #define TCSS_XHCI_USB2_PORT_NUM 10 #define TCSS_XHCI_USB3_PORT_NUM 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Gerrit-Change-Number: 55230 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
by Sridhar Siricilla (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55015 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines ...................................................................... soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines The patch configures 4KB memory region window for each of the TBT DMA remapping engine. So, the remap engines map their register set to the respective 4KB window. TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/55015/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Gerrit-Change-Number: 55015 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: rename acpi_soc_fill_bert and add return value
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55053 ) Change subject: acpi: rename acpi_soc_fill_bert and add return value ...................................................................... Patch Set 1: (1 comment) Commit Message: PS1: > adding an open comment so the patch won't be merged before Tim had a chance to verify that the patch […] This patch train is verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/55053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaa3eed51645e1b3bc904c6279d171e3a10d59be Gerrit-Change-Number: 55053 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 16:55:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi/device: Add ability to generate proper _STA for PowerResource
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55027 ) Change subject: acpi/device: Add ability to generate proper _STA for PowerResource ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91410556db002c620fd9aaa99981457808da93a5 Gerrit-Change-Number: 55027 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 16:54:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2021