June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/lenovo/t410: Update PCH PCIe RP comments
by Paul Menzel (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55171 ) Change subject: mb/lenovo/t410: Update PCH PCIe RP comments ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Gerrit-Change-Number: 55171 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:26:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Rex-BC Chen (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/6f65cc49_320e2fa4 PS1, Line 9: Fix GPIO pu/pd offset. > Do you have a reference for these offsets so we can know it's now correct? […] In file MT8195 Register Map_V0.2 -1.pdf (https://drive.google.com/drive/folders/12qTn0CBvrmV1UNyJiWNEJGEpj_OGGfzl?re…) chapter: 3.2 GPIO Controller (page3272) control register name: PUPD_CFG0 PU_CFG0 offset should be fix is which bit control GPIO PUPD/PU Detail: 3.2.2 IOCGF_LM PUPD_CFG0 (page:3347) PU_CFG0 (page:3348) 3.2.3 IOCGF_BL PU_CFG0 (page:3373) 3.2.4 IOCGF_BM PU_CFG0 (page:3400) 3.2.5 IOCGF_BR PUPD_CFG0 (page:3428) PU_CFG0 (page:3432) 3.2.6 IOCGF_RB PUPD_CFG0 (page:3456) 3.2.7 IOCGF_TL PUPD_CFG0 (page:3473) PU_CFG0 (page:3475) -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Cliff Huang, Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55150 ) Change subject: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I127c695eed9e2842996381c7559695f289cf4585 Gerrit-Change-Number: 55150 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 04:17:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Cliff Huang, Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55151 ) Change subject: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87fa55e4003e789d55ddce11d1f76e9ca8b08f18 Gerrit-Change-Number: 55151 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 04:16:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: V Sowmya, Cliff Huang, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/8280345e_986fa106 PS7, Line 16: 1536 suggestion: `PEPD_PMC_PWRM_LPM_REQ_DATA_LEN * 8` -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 04:16:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Separate SMBIOS SKU functions
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55174 ) Change subject: ec/google/chromeec: Separate SMBIOS SKU functions ...................................................................... Patch Set 1: (2 comments) File src/ec/google/chromeec/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55174/comment/02dec1d6_580f65a0 PS1, Line 17: smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_smbios_skuid.c I don't believe this is required File src/ec/google/chromeec/ec_smbios_skuid.c: PS1: suggestion: name this file `ec_smbios.c` -- To view, visit https://review.coreboot.org/c/coreboot/+/55174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8916223f5f04afe4761be4ad3313e900efae90d4 Gerrit-Change-Number: 55174 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Werner Zeh (Code Review) June 3, 2021

June 3, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55082 ) Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index be2b6c9..d6dca67 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -70,6 +70,18 @@ register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[5]" = "0x5" + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index b55884c..a522db5 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -109,6 +109,10 @@ int default 7 +config MAX_SATA_PORTS + int + default 2 + config MAX_PCIE_CLOCK_SRC int default 6 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index ebe14d5..f51e723 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -90,8 +90,22 @@ /* SATA related */ uint8_t SataMode; uint8_t SataSalpSupport; - uint8_t SataPortsEnable[8]; - uint8_t SataPortsDevSlp[8]; + uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS]; + uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS]; + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS]; + /* SataPortsDmVal is the DITO multiplier. Default is 15. */ + uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS]; + /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ + uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS]; /* Audio related */ uint8_t PchHdaDspEnable; @@ -135,6 +149,7 @@ /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; + uint8_t ScsEmmcDdr50Enabled; /* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 98c939f..f02d20e 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,6 +15,13 @@ #include <soc/soc_chip.h> #include <string.h> +/* SATA DEVSLP idle timeout default values */ +#define DEF_DMVAL 15 +#define DEF_DITOVAL_MS 625 + +/* Native function controls pads termination */ +#define GPIO_TERM_NATIVE 0x1F + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -231,6 +238,46 @@ params->PcieRpVc1TcMap[i] = 0x60; } + /* SATA config */ + dev = pcidev_path_on_root(PCH_DEVFN_SATA); + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + + for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) { + params->SataPortsEnable[i] = config->SataPortsEnable[i]; + params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i]; + if (config->SataPortsEnableDitoConfig[i]) { + params->SataPortsDmVal[i] = + config->SataPortsDmVal[i] ? : DEF_DMVAL; + params->SataPortsDitoVal[i] = + config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS; + } + } + } + + /* SDCard config */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + params->ScsSdCardEnabled = is_dev_enabled(dev); + if (params->ScsSdCardEnabled) { + params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; + params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE; + } + + /* eMMC config */ + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + params->ScsEmmcEnabled = is_dev_enabled(dev); + if (params->ScsEmmcEnabled) { + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 14 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Werner Zeh (Code Review) June 3, 2021

June 3, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55034 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 111 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index fa82a68..be2b6c9 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -27,10 +27,27 @@ # Enable DDC for DDI ports C register "DdiPortCDdc" = "1" + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" - # Enable All Root Ports (1-7) + # PCIe root ports related UPDs register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 6b36792..ebe14d5 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -80,8 +80,8 @@ uint8_t RMT; /* USB related */ - struct usb2_port_config usb2_ports[16]; - struct usb3_port_config usb3_ports[10]; + struct usb2_port_config usb2_ports[10]; + struct usb3_port_config usb3_ports[4]; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ @@ -103,16 +103,29 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; +/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + + /* Probe CLKREQ# signal before enabling CLKREQ# based power management. + * Enable - Default (0) / Disable (1) */ + uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe LTR: Enable - Default (0) / Disable (1) */ + uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 88e7d06..98c939f 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,6 +15,25 @@ #include <soc/soc_chip.h> #include <string.h> +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -99,6 +118,7 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + unsigned int i; struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_elkhartlake_config *config = config_of_soc(); @@ -154,6 +174,63 @@ /* HECI */ params->Heci3Enabled = config->Heci3Enable; + /* USB configuration */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ? + config->usb2_ports[i].ocpin : 0xff; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ? + config->usb3_ports[i].ocpin : 0xff; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + params->UsbClockGatingEnable = 1; + params->UsbPowerGatingEnable = 1; + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* PCIe root ports config */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpClkReqDetect[i] = + !config->PcieRpClkReqDetectDisable[i]; + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i]; + params->PcieRpAdvancedErrorReporting[i] = + !config->PcieRpAdvancedErrorReportingDisable[i]; + params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = config->PciePtm[i]; + params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003; + params->PcieRpLtrMaxSnoopLatency[i] = 0x1003; + /* Virtual Channel 1 to Traffic Class mapping */ + params->PcieRpVc1TcMap[i] = 0x60; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 11 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP]Allow to build romstage sources inside the bootblock
by Keith Hui (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Arthur Heymans, Martin Roth, ron minnich, Paul Menzel, Stefan Reinauer, Angel Pons, Patrick Rudolph, Ron Minnich, Felix Held. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55068 ) Change subject: [WIP]Allow to build romstage sources inside the bootblock ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > You also need to build the current patch set, as the files where only added in patch set 2 [1]. > > [1]: https://review.coreboot.org/c/coreboot/+/55067/1..2 That's it! I needed it as well. Done that. Building for asus/p2b-ls without payload yields this result: Separate romstage Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 17408 none cpu_microcode_blob.bin 0x4500 microcode 83968 none fallback/ramstage 0x18d40 stage 52312 LZMA build_info 0x25a00 raw 98 none fallback/dsdt.aml 0x25ac0 raw 5630 none cmos_layout.bin 0x27100 cmos_layout 704 none fallback/postcar 0x27400 stage 10400 none (empty) 0x29d00 null 79204 none bootblock 0x3d280 bootblock 11088 none romstage folded into bootblock Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none cpu_microcode_blob.bin 0x80 microcode 83968 none fallback/ramstage 0x148c0 stage 52312 LZMA build_info 0x21580 raw 98 none fallback/dsdt.aml 0x21640 raw 5630 none cmos_layout.bin 0x22c80 cmos_layout 704 none fallback/postcar 0x22f80 stage 10400 none (empty) 0x25880 null 88804 none bootblock 0x3b380 bootblock 19008 none For a savings of 9600 bytes. Less than the 10-20k claimed, but still significant. I look forward to further activities on the LTO front. Still I would have to leave out microcode to fit the Adaptec SCSI BIOS lifted from vendor firmware to boot from SCSI drives, or attempt to port aic78u2 to seabios (holy F!). I still have to build it with seabios with a ps/2 init patch for boot testing - I do have issues with a real Model M on ps/2 port. -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Add new Elan touchscreen
by Werner Zeh (Code Review) June 3, 2021

June 3, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54868 ) Change subject: mb/google/dedede/var/cret: Add new Elan touchscreen ...................................................................... mb/google/dedede/var/cret: Add new Elan touchscreen Add Elan eKTH7D18 touchscreen into devicetree for cret. BUG=b:180547935, b:187484857 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54868 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 2586322..82002e4 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -147,6 +147,24 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "300" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 16 on end + end end # I2C 2 device pci 15.3 off end # I2C 3 device pci 1c.7 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/54868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Gerrit-Change-Number: 54868 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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