coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
by Aseda Aboagye (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Andrey Pronin, Christian Walter, Aseda Aboagye, Aaron Durbin. Hello build bot (Jenkins), Andrey Pronin, Christian Walter, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55241 to look at the new patch set (#2). Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` ...................................................................... security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` This commit adds support for the TPM2_NV_SetBits command to the TLCL. This command is used to set bits in an NV index that was created as a bit field. Any number of bits from 0 to 64 may be set. The contents of bits are ORed with the current contents of the NV index. The following is an excerpt from lalala undergoing TPM factory initialization which exercises this function in a child commit: ``` antirollback_read_space_firmware():566: TPM: Not initialized yet. factory_initialize_tpm():530: TPM: factory initialization tlcl_self_test_full: response is 0 tlcl_force_clear: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: kernel space already exists tlcl_write: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: RO MRC Hash space already exists tlcl_write: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: FWMP space already exists tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_set_bits: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 factory_initialize_tpm():553: TPM: factory initialization successful ``` BUG=b:184676425 BRANCH=None TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the bits attribute. Issue the command and verify that the TPM command succeeds. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/55241/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 Gerrit-Change-Number: 55241 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_CPU_INIT
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55204 ) Change subject: cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_CPU_INIT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444 Gerrit-Change-Number: 55204 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 07:22:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86: Drop Kconfig PARALLEL_CPU_INIT
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55203 ) Change subject: cpu/x86: Drop Kconfig PARALLEL_CPU_INIT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019 Gerrit-Change-Number: 55203 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 07:21:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/model_2065x: Drop select PARALLEL_CPU_INIT
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55202 ) Change subject: cpu/intel/model_2065x: Drop select PARALLEL_CPU_INIT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d9f40daa4e92301d76927f73be93cb768c45d5 Gerrit-Change-Number: 55202 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 07:21:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by Lance Zhao (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Marc Jones, Nico Huber, Jonathan Zhang, Philipp Deppenwiese, Tim Wawrzynczak, Julius Werner, Angel Pons, Subrata Banik, Patrick Rudolph, Peter Tsung Ho Wu, Ron Minnich. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... Patch Set 4: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/52585/comment/ee4bdb77_26a82143 PS4, Line 158: #define LB_MEM_SOFT_RESERVED 0xefffffff /* Special-purpose memory */ > Checking with Dan now. But current lb_memory_range is not same as ACPI memory range address anyway? https://uefi.org/specs/ACPI/6.4/15_System_Address_Map_Interfaces/Sys_Addres… 6 is AddressRangeDisabled in ACPI spec -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Ron Minnich <rminnich(a)google.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 03:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by Lance Zhao (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Marc Jones, Nico Huber, Jonathan Zhang, Philipp Deppenwiese, Tim Wawrzynczak, Julius Werner, Angel Pons, Subrata Banik, Patrick Rudolph, Peter Tsung Ho Wu, Ron Minnich. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... Patch Set 4: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/52585/comment/c862199a_44a552fe PS4, Line 158: #define LB_MEM_SOFT_RESERVED 0xefffffff /* Special-purpose memory */ > It's probably best to ask Dan then? […] Checking with Dan now. -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Ron Minnich <rminnich(a)google.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 02:25:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/sm: Use device aliases
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55206 ) Change subject: mb/intel/sm: Use device aliases ...................................................................... mb/intel/sm: Use device aliases Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all shadowmountain board variants. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 40 insertions(+), 73 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 52b35fa..5b6a097 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -174,21 +174,16 @@ }" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 off end # PEG60 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 - device pci 08.0 off end # GNA - device pci 09.0 off end # NPK - device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 on + device ref igpu on end + device ref dtt on end + device ref ipu on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref crashlog off end + device ref tcss_xhci on end + device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp" = "{ [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),}, @@ -196,39 +191,31 @@ device generic 0 on end end end - device pci 0d.3 on end # TBT DMA1 - device pci 0e.0 off end # VMD - device pci 10.0 off end - device pci 10.1 off end - device pci 12.0 off end # SensorHUB - device pci 12.6 off end # GSPI2 - device pci 13.0 off end # GSPI3 - device pci 14.0 on + device ref tcss_dma1 on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" - device usb 2.9 on end + device ref usb2_port10 on end end end end - end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI - device pci 14.2 off end # Shared RAM - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi - device pci 15.0 on end # I2C0 - device pci 15.1 on end # I2C1 - device pci 15.2 on + end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -257,17 +244,11 @@ register "name" = ""MAXL"" device i2c 32 on end end - end # I2C2 - device pci 15.3 on end # I2C3 - device pci 16.0 on end # HECI1 - device pci 16.1 off end # HECI2 - device pci 16.2 off end # CSME - device pci 16.3 off end # CSME - device pci 16.4 off end # HECI3 - device pci 16.5 off end # HECI4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C4 - device pci 19.1 on + end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -276,46 +257,34 @@ register "probed" = "1" device i2c 15 on end end - end # I2C5 - device pci 19.2 off end # UART2 - device pci 1c.0 off end # RP1 - device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 - device pci 1c.4 on end # RP5 - device pci 1c.5 off end # RP6 - device pci 1c.6 off end # RP7 - device pci 1c.7 on + end + device ref pcie_rp5 on end + device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" register "srcclk_pin" = "3" device generic 0 on end end - end # RP8 - device pci 1d.0 on end # RP9 - device pci 1d.1 off end # RP10 - device pci 1d.2 off end # RP11 - device pci 1d.3 off end # RP12 - device pci 1e.0 on end # UART0 - device pci 1e.1 off end # UART1 - device pci 1e.2 on + end + device ref pcie_rp9 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)" device spi 0 on end end - end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden + end + device ref p2sb on end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -336,10 +305,8 @@ end end end - end # PMC - device pci 1f.3 on end # Intel Audio SNDW - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/55206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Gerrit-Change-Number: 55206 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/intel/adlrvp: Use device aliases
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55205 ) Change subject: mb/intel/adlrvp: Use device aliases ...................................................................... mb/intel/adlrvp: Use device aliases Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all different adlrvp boards. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb 4 files changed, 88 insertions(+), 151 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 04c3272..9def4be 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -204,10 +204,9 @@ }" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 on end # PEG10 - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref pcie5 on end + device ref igpu on end + device ref dtt on chip drivers/intel/dptf ## sensor information @@ -301,82 +300,57 @@ device generic 0 on end end - end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 06.2 on end # PEG62 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 - device pci 08.0 off end # GNA - device pci 09.0 off end # NPK - device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 - device pci 0e.0 off end # VMD - device pci 10.0 off end - device pci 10.1 off end - device pci 12.0 off end # SensorHUB - device pci 12.6 off end # GSPI2 - device pci 13.0 off end # GSPI3 - device pci 14.0 on + end + device ref ipu on end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref crashlog off end + device ref tcss_xhci on end + device ref tcss_xdci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.9 on end + device ref usb2_port10 on end end end end - end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI - device pci 14.2 off end # Shared RAM - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi - device pci 15.0 on end # I2C0 - device pci 15.1 on end # I2C1 - device pci 15.2 on end # I2C2 - device pci 15.3 on end # I2C3 - device pci 16.0 on end # HECI1 - device pci 16.1 off end # HECI2 - device pci 16.2 off end # CSME - device pci 16.3 off end # CSME - device pci 16.4 off end # HECI3 - device pci 16.5 off end # HECI4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C4 - device pci 19.1 on end # I2C5 - device pci 19.2 off end # UART2 - device pci 1c.0 on end # RP1 - device pci 1c.1 off end # RP2 - device pci 1c.2 on end # RP3 # W/A to FSP issue - device pci 1c.3 on end # RP4 # W/A to FSP issue - device pci 1c.4 on end # RP5 - device pci 1c.5 on end # RP6 - device pci 1c.6 off end # RP7 - device pci 1c.7 on end # RP8 - device pci 1d.0 on end # RP9 - device pci 1d.1 off end # RP10 - device pci 1d.2 on end # RP11 - device pci 1d.3 off end # RP12 - device pci 1e.0 on end # UART0 - device pci 1e.1 off end # UART1 - device pci 1e.2 on end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1f.0 on end # eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # PMC - device pci 1f.3 on + end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on end + device ref pcie_rp1 on end + device ref pcie_rp3 on end # W/A to FSP issue + device ref pcie_rp4 on end # W/A to FSP issue + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref hda on chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc711 @@ -386,10 +360,7 @@ end end end - end # Intel Audio SNDW - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH + end + device ref smbus on end end end diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4ebfff2..f6bd0f3 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -153,85 +153,54 @@ }" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 on end # PEG10 - device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 06.2 on end # PEG62 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 off end # TBT_PCIe2 - device pci 07.3 off end # TBT_PCIe3 - device pci 08.0 off end # GNA - device pci 09.0 off end # NPK - device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 off end # TBT DMA1 - device pci 0e.0 off end # VMD - device pci 10.0 off end - device pci 10.1 off end - device pci 12.0 off end # SensorHUB - device pci 12.6 off end # GSPI2 - device pci 13.0 off end # GSPI3 - device pci 14.0 on + device ref pcie5 on end + device ref igpu on end + device ref dtt on end + device ref ipu on end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" - device usb 0.0 on + device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.9 on end + device ref usb2_port10 on end end end end - end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI - device pci 14.2 off end # Shared RAM - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi - device pci 15.0 on end # I2C0 - device pci 15.1 on end # I2C1 - device pci 15.2 on end # I2C2 - device pci 15.3 on end # I2C3 - device pci 16.0 on end # HECI1 - device pci 16.1 off end # HECI2 - device pci 16.2 off end # CSME - device pci 16.3 off end # CSME - device pci 16.4 off end # HECI3 - device pci 16.5 off end # HECI4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C4 - device pci 19.1 on end # I2C5 - device pci 19.2 off end # UART2 - device pci 1c.0 on end # RP1 - device pci 1c.1 off end # RP2 - device pci 1c.2 on end # RP3 # W/A to FSP issue - device pci 1c.3 on end # RP4 # W/A to FSP issue - device pci 1c.4 on end # RP5 - device pci 1c.5 on end # RP6 - device pci 1c.6 off end # RP7 - device pci 1c.7 on end # RP8 - device pci 1d.0 on end # RP9 - device pci 1d.1 on end # RP10 - device pci 1d.2 off end # RP11 - device pci 1d.3 off end # RP12 - device pci 1e.0 on end # UART0 - device pci 1e.1 off end # UART1 - device pci 1e.2 on end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1f.0 on end # eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # PMC - device pci 1f.3 on + end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on end + device ref pcie_rp1 on end + device ref pcie_rp3 on end # W/A to FSP issue + device ref pcie_rp4 on end # W/A to FSP issue + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref hda on chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc711 @@ -241,10 +210,7 @@ end end end - end # Intel Audio SNDW - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH + end + device ref smbus on end end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 68a1bfa..133a737 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -1,13 +1,13 @@ chip soc/intel/alderlake device domain 0 on - device pci 1f.0 on + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI - device pci 1f.2 hidden + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -29,6 +29,6 @@ end end end - end # PMC + end end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index 9130a12..bfc8991 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -1,15 +1,15 @@ chip soc/intel/alderlake device domain 0 on - device pci 1f.0 on + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] use conn2 as mux_conn[2] device pnp 0c09.0 on end end - end # eSPI - device pci 1f.2 hidden + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -37,6 +37,6 @@ end end end - end # PMC + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/55205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Gerrit-Change-Number: 55205 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: include: always unsigned long for size_t
by Nico Huber (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Paul Menzel, Julius Werner, Jacob Garber. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55075 ) Change subject: include: always unsigned long for size_t ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Yeah, now I understand what that stuff actually does. […] size_t and ptrdiff_t are part of the language (there are operators that return these types). The stdint types and (u)intptr_t are only specified in the library. But if GCC provides a macro for the latter, I guess it makes sense to use that too. -- To view, visit https://review.coreboot.org/c/coreboot/+/55075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8fa97c6961991dd8e291d2dc7d8762f83cad6d Gerrit-Change-Number: 55075 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Sat, 05 Jun 2021 19:43:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by David Wu (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: David Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55249 to look at the new patch set (#3). Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... mb/google/dedede/var/metaknight: Turn off lte power when s0ix Turn off lte power when s0ix for power saving. BUG=b:188614547 TEST= measure lte power comsumption is 0mV under s0ix Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55249/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021