coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by David Wu (Code Review) 05 Jun '21

05 Jun '21

David Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/55249 ) Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... mb/google/dedede/var/metaknight: Turn off lte power when s0ix Turn off lte power when s0ix for power saving. BUG=b:188614547 TEST= measure lte power comsumption is 0mV under s0ix Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55249/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by David Wu (Code Review) 05 Jun '21

05 Jun '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55249 ) Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... mb/google/dedede/var/metaknight: Turn off lte power when s0ix Turn off lte power when s0ix for power saving. BUG=b:188614547 TEST= measure lte power comsumption is 0mV under s0ix Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55249/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e1bc9ad..3e68e9b 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -149,6 +149,12 @@ default "pirika" if BOARD_GOOGLE_PIRIKA default "haboki" if BOARD_GOOGLE_HABOKI +config VARIANT_HAS_LTE_ACPI + bool + default n + help + Select this option to enable lte ACPI support on the variant. + endif #BOARD_GOOGLE_BASEBOARD_DEDEDE if BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 3f2c522..0d558c1 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -91,6 +91,7 @@ bool "-> Metaknight" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP + select VARIANT_HAS_LTE_ACPI config BOARD_GOOGLE_LANTIS bool "-> Lantis" diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index f88e2df..344fda7 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -35,6 +35,11 @@ #include <variant/acpi/camera.asl> #endif +#if CONFIG(VARIANT_HAS_LTE_ACPI) + /* LTE */ + #include <variant/acpi/lte.asl> +#endif + #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl b/src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl new file mode 100644 index 0000000..1e76e17 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define LTE_EN GPP_A10 /* Active High */ + +/* Method called from PEPD prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off lte power */ + \_SB.PCI0.STXS (LTE_EN) + } Else { + /* Turn on lte power */ + \_SB.PCI0.CTXS (LTE_EN) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55221 ) Change subject: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb ...................................................................... mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 3 files changed, 0 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 23913cc..04c3272 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -319,19 +319,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4e4135f..4ebfff2 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -174,19 +174,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 43a23a1..52b35fa 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -200,19 +200,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Gerrit-Change-Number: 55221 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add IDE-R and KT device into chipset.cb
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55209 ) Change subject: soc/intel/alderlake: Add IDE-R and KT device into chipset.cb ...................................................................... soc/intel/alderlake: Add IDE-R and KT device into chipset.cb Add IDE-R and KT device to chipset.cb and leave it off by default. Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55209 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 53d75e4..c51f92c 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -121,6 +121,8 @@ device pci 15.3 alias i2c3 off end device pci 16.0 alias heci1 off end device pci 16.1 alias heci2 off end + device pci 16.2 alias ide_r off end + device pci 16.3 alias kt off end device pci 16.4 alias heci3 off end device pci 16.5 alias heci4 off end device pci 17.0 alias sata off end -- To view, visit https://review.coreboot.org/c/coreboot/+/55209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98 Gerrit-Change-Number: 55209 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Angel Pons (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 15: (10 comments) Patchset: PS15: > Does this mean the patch has to submitted again? Yes. I would create a separate change for the KBL and the CML boards, which should be easier to review. With the current state of affairs, using a variant setup with different SoCs is too impractical. I'd do something like what Purism does: mb/starlabs/labtop_kbl and mb/starlabs/labtop_cml. PS15: Looks like I forgot to send these comments File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/55128/comment/a5e42e4b_98e03efb PS15, Line 26: # select HAVE_IFD_BIN : # select HAVE_ME_BIN > Nope. See previous comment. Which one is the previous comment? File src/mainboard/starlabs/labtop/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/55128/comment/20676505_49e6aab7 PS15, Line 6: /* Power button device. */ : Device (PWRB) : { : Name (_HID, EisaId ("PNP0C0C")) : Name (PBST, One) : : Method (_STA, 0, NotSerialized) : { : Return (0x0F) : } : } > For what reason? See ACPI spec, section 4.8.2.2.1 Power Button The fixed power button should be good enough. I recall having a PWRB device in ASL caused two power button devices to appear. CB:27272 has a good explanation about it. File src/mainboard/starlabs/labtop/mainboard.c: https://review.coreboot.org/c/coreboot/+/55128/comment/928e9402_7b30369c PS15, Line 33: #if CONFIG(BOARD_STARLABS_LABTOP_CML) > How? Just use C code, and let the compiler optimise out the unreachable paths: if (CONFIG(BOARD_STARLABS_LABTOP_CML)) return "L4"; else return "L3-U"; endif https://review.coreboot.org/c/coreboot/+/55128/comment/6366463c_9a331925 PS15, Line 52: /* Override smbios_mainboard_board_type */ : smbios_board_type smbios_mainboard_board_type(void) : { : return SMBIOS_BOARD_TYPE_MOTHERBOARD; : } > Why? It's the default board type since CB:50180 File src/mainboard/starlabs/labtop/ramstage.c: https://review.coreboot.org/c/coreboot/+/55128/comment/e8b18f5d_d25e16f6 PS15, Line 10: #if CONFIG(BOARD_STARLABS_LABTOP_CML) > Is there any advantage? Not being difficult, simply interested. It's cleaner. Plus, FSP likes to reconfigure GPIOs: having coreboot configure GPIOs after FSP is done can prevent weird issues if FSP decides it knows better. File src/mainboard/starlabs/labtop/variants/cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55128/comment/2cb0907b_9018fc56 PS15, Line 140: device pci 00.0 on end > It will always be present on our hardware, can remove though I would remove it for the sake of correctness. The only difference it makes is that the `on_mainboard` field of the device gets unset. File src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h: https://review.coreboot.org/c/coreboot/+/55128/comment/00a34c34_73ea9eb1 PS15, Line 36: /* ONE DOES NOT SIMPLY : MAKE IT WORK WITH WINDOWS */ > A comment is necassary. […] Well, we can have the best of both worlds: the helpful reasoning and the meme 😉 File src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55128/comment/c954dec1_21e8fd51 PS15, Line 24: .up_delay_ms= 200,// T3 : .down_delay_ms= 0,// T10 : .cycle_delay_ms = 500,// T12 : .backlight_on_delay_ms=50,// T7 : .backlight_off_delay_ms = 0,// T9 : .backlight_pwm_hz = 200, > As far as I know, nit is an achaic term for brightness of a display. […] In the context of code reviews, it means something is a minor issue. This one, for instance, is just a matter of aesthetics. I... honestly don't know where this meaning of "nit" comes from, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Sat, 05 Jun 2021 14:08:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Andy Pont (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Sean Rhodes. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 15: (3 comments) File src/mainboard/starlabs/labtop/mainboard.c: https://review.coreboot.org/c/coreboot/+/55128/comment/1d4b3640_97d7391a PS15, Line 33: #if CONFIG(BOARD_STARLABS_LABTOP_CML) > How? if (CONFIG(BOARD_STARLABS_LABTOP_CML)) return "L4"; else return "L3-U"; https://review.coreboot.org/c/coreboot/+/55128/comment/4d78cb3d_15bae972 PS15, Line 52: /* Override smbios_mainboard_board_type */ : smbios_board_type smbios_mainboard_board_type(void) : { : return SMBIOS_BOARD_TYPE_MOTHERBOARD; : } > Why? When this file was originally created this function returned SMBIOS_BOARD_TYPE_UNKNOWN. As of commit d37cfb7 it was changed to SMBIOS_BOARD_TYPE_MOTHERBOARD and no longer needs to be overridden. File src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55128/comment/1a10a42a_6b5c118f PS15, Line 24: .up_delay_ms= 200,// T3 : .down_delay_ms= 0,// T10 : .cycle_delay_ms = 500,// T12 : .backlight_on_delay_ms=50,// T7 : .backlight_off_delay_ms = 0,// T9 : .backlight_pwm_hz = 200, > As far as I know, nit is an achaic term for brightness of a display. […] Short for "nit-pick"! Have a look at src/mainboard/51nb/x210/devicetree.cb all the equals signs and hence the comments are aligned. -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Sat, 05 Jun 2021 14:06:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Change ELAN touchpad driver
by Zhi7 Li (Code Review) 05 Jun '21

05 Jun '21

Zhi7 Li has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/55248 ) Change subject: mb/google/dedede/var/sasukette: Change ELAN touchpad driver ...................................................................... mb/google/dedede/var/sasukette: Change ELAN touchpad driver Change ELAN touchpad devicetree config for touchpad firmware update. BUG=b:188602529 BRANCH=dedede TEST=built sasukette firmware and verified Signed-off-by: lizhi7 <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55248/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Gerrit-Change-Number: 55248 Gerrit-PatchSet: 2 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Change ELAN touchpad driver
by Zhi7 Li (Code Review) 05 Jun '21

05 Jun '21

Zhi7 Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55248 ) Change subject: mb/google/dedede/var/sasukette: Change ELAN touchpad driver ...................................................................... mb/google/dedede/var/sasukette: Change ELAN touchpad driver Change ELAN touchpad devicetree config for touchpad firmware update. BUG=b:188602529 BRANCH=dedede TEST=built sasukette firmware and verified Signed-off-by: lizhi7 <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55248/1 diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 0f48365..4a54667 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -127,12 +127,12 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end - chip drivers/i2c/hid - register "generic.hid" = ""ELAN0000"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.wake" = "GPE0_DW0_03" - register "generic.probed" = "1" + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" device i2c 15 on end end end #I2C 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/55248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Gerrit-Change-Number: 55248 Gerrit-PatchSet: 1 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com> Change-...
by Zhi7 Li (Code Review) 05 Jun '21

05 Jun '21

Zhi7 Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55247 ) Change subject: Signed-off-by: lizhi7 <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: I2e4862eeebb2557470560ee647cdec063e0f3428 ...................................................................... Signed-off-by: lizhi7 <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: I2e4862eeebb2557470560ee647cdec063e0f3428 Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55247/1 diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 0f48365..4a54667 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -127,12 +127,12 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end - chip drivers/i2c/hid - register "generic.hid" = ""ELAN0000"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.wake" = "GPE0_DW0_03" - register "generic.probed" = "1" + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" device i2c 15 on end end end #I2C 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/55247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Gerrit-Change-Number: 55247 Gerrit-PatchSet: 1 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offsets
by Hung-Te Lin (Code Review) 05 Jun '21

05 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offsets ...................................................................... soc/mediatek/mt8195: fix GPIO register offsets Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 Signed-off-by: Zhiqiang Ma <zhiqiang.ma(a)mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/include/soc/gpio.h 1 file changed, 43 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 0739f63..e5c1ff1 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -56,40 +56,40 @@ PIN(5, GPIO_05, 1, 5, 0x23, 0x60, TP_GPIO5_AO, MSDC2_DAT1, SPDIF_IN0, URXD3, SCL2, RES6, USB_DRVVBUS_2P), - PIN(6, GPIO_06, 0, 6, 0x23, 0x70, + PIN(6, GPIO_06, 0, 0, 0x23, 0x70, TP_GPIO6_AO, DP_TX_HPD, I2SO1_D4, UTXD4, CMVREF3, RES6, DMIC3_CLK), - PIN(7, GPIO_07, 0, 7, 0x23, 0x70, + PIN(7, GPIO_07, 0, 1, 0x23, 0x70, TP_GPIO7_AO, EDP_TX_HPD, I2SO1_D5, URXD4, CMVREF4, RES6, DMIC3_DAT), - PIN(8, SDA0, 0, 13, 0x23, 0x70, + PIN(8, SDA0, 0, 7, 0x23, 0x70, SDA0, PWM_0, RES3, SPDIF_OUT, RES5, LVTS_FOUT, DBG_MON_A0), - PIN(9, SCL0, 0, 8, 0x23, 0x70, + PIN(9, SCL0, 0, 2, 0x23, 0x70, SCL0, PWM_1, RES3, IR_IN, RES5, LVTS_SDO, DBG_MON_A1), - PIN(10, SDA1, 0, 14, 0x23, 0x70, + PIN(10, SDA1, 0, 8, 0x23, 0x70, SDA1, PWM_2, ADSP_URXD0, SPDIF_IN1, RES5, LVTS_SCF, DBG_MON_A2), - PIN(11, SCL1, 0, 9, 0x23, 0x70, + PIN(11, SCL1, 0, 3, 0x23, 0x70, SCL1, PWM_3, ADSP_UTXD0, SPDIF_IN0, RES5, LVTS_SCK, DBG_MON_A3), - PIN(12, SDA2, 0, 15, 0x23, 0x70, + PIN(12, SDA2, 0, 9, 0x23, 0x70, SDA2, DMIC3_DAT_R, I2SO1_D6, RES4, RES5, LVTS_SDI, DBG_MON_A4), - PIN(13, SCL2, 0, 10, 0x23, 0x70, + PIN(13, SCL2, 0, 4, 0x23, 0x70, SCL2, DMIC4_DAT_R, I2SO1_D7, RES4, RES5, RES6, DBG_MON_A5), - PIN(14, SDA3, 0, 16, 0x23, 0x70, + PIN(14, SDA3, 0, 10, 0x23, 0x70, SDA3, DMIC3_DAT, TDMIN_MCK, RES4, RES5, RES6, DBG_MON_A6), - PIN(15, SCL3, 0, 11, 0x23, 0x70, + PIN(15, SCL3, 0, 5, 0x23, 0x70, SCL3, DMIC3_CLK, TDMIN_DI, RES4, RES5, RES6, DBG_MON_A7), - PIN(16, SDA4, 0, 17, 0x23, 0x70, + PIN(16, SDA4, 0, 11, 0x23, 0x70, SDA4, DMIC4_DAT, TDMIN_LRCK, RES4, RES5, RES6, DBG_MON_A8), - PIN(17, SCL4, 0, 12, 0x23, 0x70, + PIN(17, SCL4, 0, 6, 0x23, 0x70, SCL4, DMIC4_CLK, TDMIN_BCK, RES4, RES5, RES6, DBG_MON_A9), PIN(18, DPTX_HPD, 0, 5, 0x10, 0x60, @@ -170,10 +170,10 @@ PIN(43, PWRAP_SPI_MI, 0, 9, 0x21, 0xb0, PWRAP_SPI0_MI, PWRAP_SPI0_MO, SPIM3_MI, RES4, RES5, RES6, DBG_MON_B1), - PIN(44, SPMI_M_SCL, 0, 20, 0x21, 0xb0, + PIN(44, SPMI_M_SCL, 0, 21, 0x21, 0xb0, SPMI_M_SCL, I2SI00_DATA1, SCL5, UTXD5, RES5, RES6, DBG_MON_B2), - PIN(45, SPMI_M_SDA, 0, 21, 0x21, 0xb0, + PIN(45, SPMI_M_SDA, 0, 22, 0x21, 0xb0, SPMI_M_SDA, I2SI00_DATA2, SDA5, URXD5, RES5, RES6, DBG_MON_B3), PIN(46, I2SIN_MCK, 0, 18, 0x21, 0xa0, @@ -329,43 +329,43 @@ PIN(96, DGI_CK, 1, 0, 0x22, 0x60, DGI_CK, DPI_CK, URXD2, I2SO5_MCK, I2SIN_D2, CCU0_JTAG_TRST, RES7), - PIN(97, DISP_PWM0, 0, 20, 0x22, 0x70, + PIN(97, DISP_PWM0, 0, 0, 0x22, 0x70, DISP_PWM0, DVFSRC_EXT_REQ, RES3, RES4, RES5, RES6, RES7), - PIN(98, UART0_TXD, 0, 28, 0x22, 0x70, + PIN(98, UART0_TXD, 0, 4, 0x22, 0x70, UTXD0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(99, UART0_RXD, 0, 27, 0x22, 0x70, + PIN(99, UART0_RXD, 0, 3, 0x22, 0x70, URXD0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(100, UART1_RTS, 0, 30, 0x22, 0x70, + PIN(100, UART1_RTS, 0, 6, 0x22, 0x70, URTS1, DSI_TE, I2SO1_D8, KPROW2, PWM_0, TP_URTS1_AO, I2SIN_D0), - PIN(101, UART1_CTS, 0, 29, 0x22, 0x70, + PIN(101, UART1_CTS, 0, 5, 0x22, 0x70, UCTS1, DSI1_TE, I2SO1_D9, KPCOL2, PWM_1, TP_UCTS1_AO, I2SIN_D1), - PIN(102, UART1_TXD, 0, 0, 0x22, 0x70, + PIN(102, UART1_TXD, 0, 8, 0x22, 0x70, UTXD1, VBUSVALID_2P, I2SO1_D10, SSPM_UTXD_AO, TP_UTXD1_AO, MD32_1_TXD, I2SIN_D2), - PIN(103, UART1_RXD, 0, 31, 0x22, 0x70, + PIN(103, UART1_RXD, 0, 7, 0x22, 0x70, URXD1, VBUSVALID_3P, I2SO1_D11, SSPM_URXD_AO, TP_URXD1_AO, MD32_1_RXD, I2SIN_D3), - PIN(104, KPROW0, 1, 25, 0x22, 0x60, + PIN(104, KPROW0, 1, 22, 0x22, 0x60, KPROW0, DISP_PWM1, RES3, RES4, RES5, RES6, RES7), - PIN(105, KPROW1, 1, 26, 0x22, 0x60, + PIN(105, KPROW1, 1, 23, 0x22, 0x60, KPROW1, EDP_TX_HPD, PWM_2, RES4, RES5, RES6, RES7), - PIN(106, KPCOL0, 1, 23, 0x22, 0x60, + PIN(106, KPCOL0, 1, 20, 0x22, 0x60, KPCOL0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(107, KPCOL1, 1, 24, 0x22, 0x60, + PIN(107, KPCOL1, 1, 21, 0x22, 0x60, KPCOL1, DSI1_TE, PWM_3, SCP_SCL3, I2SIN_MCK, RES6, RES7), - PIN(108, DSI_LCM_RST, 0, 22, 0x22, 0x70, + PIN(108, DSI_LCM_RST, 0, 2, 0x22, 0x70, LCM_RST, KPCOL1, RES3, SCP_SDA3, I2SIN_BCK, RES6, RES7), - PIN(109, DSI_DSI_TE, 0, 21, 0x22, 0x70, + PIN(109, DSI_DSI_TE, 0, 1, 0x22, 0x70, DSI_TE, I2SIN_D3, RES3, RES4, I2SIN_WS, RES6, RES7), PIN(110, MSDC1_CMD, 1, 1, 0x14, 0x20, @@ -421,52 +421,52 @@ PIN(127, EMMC_DSL, 1, 10, 0x25, 0x50, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(128, USB_IDDIG, 0, 3, 0x22, 0x70, + PIN(128, USB_IDDIG, 0, 11, 0x22, 0x70, IDDIG, UCTS2, UTXD5, UFS_MPHY_SCL, mbistreaden_trigger, MD32_1_GPIO0, SCP_SCL2), - PIN(129, USB_DRV_VBUS, 0, 1, 0x22, 0x70, + PIN(129, USB_DRV_VBUS, 0, 9, 0x22, 0x70, SB_DRVVBUS, URTS2, URXD5, UFS_MPHY_SDA, mbistwriteen_trigger, MD32_1_GPIO1, SCP_SDA2), - PIN(130, USB_IDDIG_1P, 0, 4, 0x22, 0x70, + PIN(130, USB_IDDIG_1P, 0, 12, 0x22, 0x70, IDDIG_1P, SPINOR_IO2, SNFI_WP, VPU_UDI_NTRST, RES5, RES6, RES7), - PIN(131, USB_DRV_VBUS_1P, 0, 2, 0x22, 0x70, + PIN(131, USB_DRV_VBUS_1P, 0, 10, 0x22, 0x70, USB_DRVVBUS_1P, SPINOR_IO3, SNFI_HOLD, MD32_1_JTAG_TRST, SCP_JTAG0_TRSTN, APU_JTAG_TRST, RES7), - PIN(132, SPIM0_CSB, 0, 13, 0x25, 0x60, + PIN(132, SPIM0_CSB, 0, 1, 0x25, 0x60, SPIM0_CSB, SCP_SPI0_CS, SPIS0_CSB, VPU_UDI_TMS, RES5, I2SO5_D0, RES7), - PIN(133, SPIM0_CLK, 0, 12, 0x25, 0x60, + PIN(133, SPIM0_CLK, 0, 0, 0x25, 0x60, SPIM0_CLK, SCP_SPI0_CK, SPIS0_CLK, VPU_UDI_TCK, RES5, I2SO5_BCK, RES7), - PIN(134, SPIM0_MO, 0, 15, 0x25, 0x60, + PIN(134, SPIM0_MO, 0, 3, 0x25, 0x60, SPIM0_MO, SCP_SPI0_MO, SPIS0_SI, VPU_UDI_TDO, RES5, I2SO5_WS, RES7), - PIN(135, SPIM0_MI, 0, 14, 0x25, 0x60, + PIN(135, SPIM0_MI, 0, 2, 0x25, 0x60, SPIM0_MI, SCP_SPI0_MI, SPIS0_SO, VPU_UDI_TDI, RES5, I2SO5_MCK, RES7), - PIN(136, SPIM1_CSB, 0, 13, 0x21, 0xb0, + PIN(136, SPIM1_CSB, 0, 14, 0x21, 0xb0, SPIM1_CSB, SCP_SPI1_A_CS, SPIS1_CSB, MD32_1_JTAG_TMS, SCP_JTAG0_TMS, APU_JTAG_TMS, DBG_MON_A15), - PIN(137, SPIM1_CLK, 0, 12, 0x21, 0xb0, + PIN(137, SPIM1_CLK, 0, 13, 0x21, 0xb0, SPIM1_CLK, SCP_SPI1_A_CK, SPIS1_CLK, MD32_1_JTAG_TCK, SCP_JTAG0_TCK, APU_JTAG_TCK, DBG_MON_A14), - PIN(138, SPIM1_MO, 0, 15, 0x21, 0xb0, + PIN(138, SPIM1_MO, 0, 16, 0x21, 0xb0, SPIM1_MO, SCP_SPI1_A_MO, SPIS1_SI, MD32_1_JTAG_TDO, SCP_JTAG0_TDO, APU_JTAG_TDO, DBG_MON_A16), - PIN(139, SPIM1_MI, 0, 14, 0x21, 0xb0, + PIN(139, SPIM1_MI, 0, 15, 0x21, 0xb0, SPIM1_MI, SCP_SPI1_A_MI, SPIS1_SO, MD32_1_JTAG_TDI, SCP_JTAG0_TDI, APU_JTAG_TDI, DBG_MON_A17), - PIN(140, SPIM2_CSB, 0, 17, 0x21, 0xb0, + PIN(140, SPIM2_CSB, 0, 18, 0x21, 0xb0, SPIM2_CSB, SPINOR_CS, SNFI_CS, DMIC3_DAT, RES5, RES6, DBG_MON_A11), - PIN(141, SPIM2_CLK, 0, 16, 0x21, 0xb0, + PIN(141, SPIM2_CLK, 0, 17, 0x21, 0xb0, SPIM2_CLK, SPINOR_CK, SNFI_CLK, DMIC3_CLK, RES5, RES6, DBG_MON_A10), - PIN(142, SPIM2_MO, 0, 19, 0x21, 0xb0, + PIN(142, SPIM2_MO, 0, 20, 0x21, 0xb0, SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT, RES5, RES6, DBG_MON_A12), - PIN(143, SPIM2_MI, 0, 18, 0x21, 0xb0, + PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0, PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, RES5, RES6, DBG_MON_A13), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2021