coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/cherry: Get RAM code from ADC
by Hung-Te Lin (Code Review) 05 Jun '21

05 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55156 ) Change subject: mb/google/cherry: Get RAM code from ADC ...................................................................... mb/google/cherry: Get RAM code from ADC On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Cherry the RAM code can be read from ADC channel 2 and 3. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55156 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/boardid.c 1 file changed, 59 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/boardid.c b/src/mainboard/google/cherry/boardid.c index 34d7692..a51eee8 100644 --- a/src/mainboard/google/cherry/boardid.c +++ b/src/mainboard/google/cherry/boardid.c @@ -1,8 +1,66 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> + +#define ADC_LEVELS 12 + +enum { + /* RAM IDs */ + RAM_ID_HIGH_CHANNEL = 3, + RAM_ID_LOW_CHANNEL = 2, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [RAM_ID_LOW_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } + + return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/55156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9 Gerrit-Change-Number: 55156 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Enable mt8195 auxadc
by Hung-Te Lin (Code Review) 05 Jun '21

05 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55155 ) Change subject: soc/mediatek/mt8195: Enable mt8195 auxadc ...................................................................... soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma(a)mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/auxadc.h A src/soc/mediatek/mt8195/include/soc/efuse.h 4 files changed, 44 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 3bdb47c..e053638 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c @@ -12,6 +13,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-y += ../common/i2c.c i2c.c @@ -20,6 +22,7 @@ verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c romstage-y += ../common/dram_init.c @@ -44,6 +47,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c +ramstage-y += ../common/auxadc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index e5195ca..f94410d 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -50,8 +50,8 @@ DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, - AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01001100, + AUXADC_BASE = IO_PHYS + 0x01002000, PERICFG_AO_BASE = IO_PHYS + 0x01003000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8195/include/soc/auxadc.h b/src/soc/mediatek/mt8195/include/soc/auxadc.h new file mode 100644 index 0000000..63c8c7c --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/auxadc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_AUXADC_H +#define SOC_MEDIATEK_MT8195_AUXADC_H + +#include <soc/auxadc_common.h> +#include <soc/infracfg.h> +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8195_infracfg_ao_regs *const mtk_infracfg = mt8195_infracfg_ao; + +#endif diff --git a/src/soc/mediatek/mt8195/include/soc/efuse.h b/src/soc/mediatek/mt8195/include/soc/efuse.h new file mode 100644 index 0000000..360a411 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/efuse.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_MEDIATEK_MT8195_EFUSE_H +#define SOC_MEDIATEK_MT8195_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t reserved[130]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x208); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Gerrit-Change-Number: 55155 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Initialize SPM
by Hung-Te Lin (Code Review) 05 Jun '21

05 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55154 ) Change subject: mb/google/cherry: Initialize SPM ...................................................................... mb/google/cherry: Initialize SPM This patch adds support for SPM. This adds 43ms to the boot time. TEST=program counter of SPM is correct value after booting up. Signed-off-by: Dawei Chien <dawei.chien(a)mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang(a)mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55154 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/mainboard.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 2607a2d..04f4293 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -11,6 +11,7 @@ #include <soc/i2c.h> #include <soc/mt6360.h> #include <soc/regulator.h> +#include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" @@ -124,6 +125,9 @@ configure_sdcard(); setup_usb_host(); + if (spm_init()) + printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); + register_reset_to_bl31(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Gerrit-Change-Number: 55154 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by Nico Huber (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Lance Zhao, Marc Jones, Jonathan Zhang, Philipp Deppenwiese, Tim Wawrzynczak, Julius Werner, Angel Pons, Subrata Banik, Patrick Rudolph, Peter Tsung Ho Wu, Ron Minnich. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... Patch Set 4: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/52585/comment/7e6a9317_65adfde8 PS4, Line 158: #define LB_MEM_SOFT_RESERVED 0xefffffff /* Special-purpose memory */ > I am not sure if it is reserved for future ACPI specification. […] It's probably best to ask Dan then? Without further information, it's wrong wrt. ACPI. -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Ron Minnich <rminnich(a)google.com> Gerrit-Comment-Date: Sat, 05 Jun 2021 12:01:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Use array for PCIe ASPM overrides
by Michael Niewöhner (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55246 ) Change subject: sb/intel/bd82x6x: Use array for PCIe ASPM overrides ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Gerrit-Change-Number: 55246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Jun 2021 10:42:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Use array for PCIe ASPM overrides
by Angel Pons (Code Review) 05 Jun '21

05 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55246 ) Change subject: sb/intel/bd82x6x: Use array for PCIe ASPM overrides ...................................................................... sb/intel/bd82x6x: Use array for PCIe ASPM overrides Using an array reduces the amount of boilerplate code. Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/pcie.c 4 files changed, 4 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/55246/1 diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 7cdb8a3..4c03c62 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -74,7 +74,7 @@ device pci 1c.1 on end # PCIe Port #2 (ETH0) device pci 1c.2 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1ec596e..914ab60 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -76,7 +76,7 @@ device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (WLAN) device pci 1c.2 on end # PCIe Port #3 (Card Reader) - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 (LAN) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 45f1226..ac29944 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -61,14 +61,7 @@ uint8_t pcie_port_coalesce; /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; + uint8_t pcie_aspm[8]; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 8513390..399c73a 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -162,32 +162,7 @@ pci_or_config32(dev, 0xd4, 1 << 1); /* Check for a rootport ASPM override */ - switch (PCI_FUNC(dev->path.pci.devfn)) { - case 0: - apmc = config->pcie_aspm_f0; - break; - case 1: - apmc = config->pcie_aspm_f1; - break; - case 2: - apmc = config->pcie_aspm_f2; - break; - case 3: - apmc = config->pcie_aspm_f3; - break; - case 4: - apmc = config->pcie_aspm_f4; - break; - case 5: - apmc = config->pcie_aspm_f5; - break; - case 6: - apmc = config->pcie_aspm_f6; - break; - case 7: - apmc = config->pcie_aspm_f7; - break; - } + apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)]; /* Setup the override or get the real ASPM setting */ if (apmc) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Gerrit-Change-Number: 55246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Hook up FSP repository
by Angel Pons (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Srinidhi N Kaushik, Raj Astekar, Nathaniel L Desimone. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48713 ) Change subject: soc/intel/tigerlake: Hook up FSP repository ...................................................................... Patch Set 15: (2 comments) File src/mainboard/google/volteer/Kconfig: https://review.coreboot.org/c/coreboot/+/48713/comment/131a309e_51cc5237 PS15, Line 23: FSP_TYPE_CLIENT > Since the default FSP type is FSP_TYPE_CLIENT, there is no need to explicitly select this at the mai […] I agree. File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/48713/comment/a35e112b_e4986598 PS15, Line 220: depends on HAVE_INTEL_FSP_REPO > This is not really a dependency, right? `HAVE_INTEL_FSP_REPO` is always selected now, so we might as well remove the dependency. -- To view, visit https://review.coreboot.org/c/coreboot/+/48713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7 Gerrit-Change-Number: 48713 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Sat, 05 Jun 2021 09:21:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up FSP repository
by Angel Pons (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Srinidhi N Kaushik, Raj Astekar, Nathaniel L Desimone. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48713 ) Change subject: soc/intel/tigerlake: Hook up FSP repository ...................................................................... Patch Set 15: Code-Review+1 (1 comment) File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/48713/comment/96ffff6c_287f57a6 PS15, Line 226: default y > ``` […] Even shorter: default !FSP_TYPE_IOT -- To view, visit https://review.coreboot.org/c/coreboot/+/48713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7 Gerrit-Change-Number: 48713 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Sat, 05 Jun 2021 09:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] pc80/rtc/option: Move register backup for SMI
by Angel Pons (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Kyösti Mälkki, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49253 ) Change subject: [RFC] pc80/rtc/option: Move register backup for SMI ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/drivers/pc80/rtc/option.c: https://review.coreboot.org/c/coreboot/+/49253/comment/b92fee6f_45d73f14 PS7, Line 122: cmos_backup_idx(); > "Datasheet says this register is write-only. […] Some southbridges use 0x74 to read the contents of 0x70, but the NMI enable bit gets lost. Not sure if NMIs ever worked. -- To view, visit https://review.coreboot.org/c/coreboot/+/49253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025e9952a949834755f5cbc3dfe7b26ab9aaa032 Gerrit-Change-Number: 49253 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 05 Jun 2021 09:18:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE
by Kyösti Mälkki (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Wonkyu Kim. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55073 ) Change subject: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Checking x2APIC mode is also in asembly code. > if we want to use Kconfig, we also need to change it. > For detail, refer https://review.coreboot.org/c/coreboot/+/52696/6/src/cpu/x86/smm/smm_stub.S SMI handler cannot assume APIC operation mode stays the same as coreboot runtime. A single location with a couple assembly instructions, guarding that with preprocessor seems unnecessary noise to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/55073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Gerrit-Change-Number: 55073 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Sat, 05 Jun 2021 08:58:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021