coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Do not call lapicid() without SMP
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55244 ) Change subject: arch/x86: Do not call lapicid() without SMP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e0f42641ca15d177590d1696475054eda6ce125 Gerrit-Change-Number: 55244 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 11:58:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Avoid aliasing MMIO writes
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55200 ) Change subject: cpu/x86/lapic: Avoid aliasing MMIO writes ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75440cb0742eeaa140f49e7e4a4c51a96465441b Gerrit-Change-Number: 55200 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 11:58:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/hyperthreading: Build only for selected models
by Arthur Heymans (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55201 ) Change subject: cpu/intel/hyperthreading: Build only for selected models ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6 Gerrit-Change-Number: 55201 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 11:56:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update binutils to 2.36.1
by Iru Cai (vimacs) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Idwer Vollering. Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54049 ) Change subject: util/crossgcc: Update binutils to 2.36.1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > i386-elf-ld.bfd: Error: unable to disambiguate: -nostartfiles (did you mean --nostartfiles ?) […] I think the all options for ld(1) are in ld/lexsup.c of binutils code. -- To view, visit https://review.coreboot.org/c/coreboot/+/54049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b Gerrit-Change-Number: 54049 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 08:17:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Use array for PCIe ASPM overrides
by Paul Menzel (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55246 ) Change subject: sb/intel/bd82x6x: Use array for PCIe ASPM overrides ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Gerrit-Change-Number: 55246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 08:10:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update binutils to 2.36.1
by Iru Cai (vimacs) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Idwer Vollering. Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54049 ) Change subject: util/crossgcc: Update binutils to 2.36.1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: i386-elf-ld.bfd: Error: unable to disambiguate: -nostartfiles (did you mean --nostartfiles ?) From ld(1), -nostartfiles is not an option of ld, while the gcc(1) driver has this option. -- To view, visit https://review.coreboot.org/c/coreboot/+/54049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b Gerrit-Change-Number: 54049 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 08:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add support for ZTE spaces
by Aseda Aboagye (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Aaron Durbin. Hello build bot (Jenkins), Andrey Pronin, Julius Werner, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55242 to look at the new patch set (#4). Change subject: security/vboot: Add support for ZTE spaces ...................................................................... security/vboot: Add support for ZTE spaces This commit adds support for the Chrome OS Zero-Touch Enrollment related spaces. For TPM 2.0 devices which don't use Cr50, coreboot will define the RMA+SN Bits, Board ID, and RMA Bytes counter spaces. The RMA+SN Bits space is 16 bytes initialized to all 0xFFs. The Board ID space is 12 bytes initialized to all 0xFFs. The RMA Bytes counter space is 8 bytes intialized to 0. BUG=b:184676425 BRANCH=None TEST=Build and flash lalala, verify that the ZTE spaces are created successfully by undefining the firmware antirollback space in the TPM such that the TPM undergoes factory initialization in coreboot. Reboot the DUT. Boot to CrOS and run `tpm_manager_client list_spaces` and verify that the ZTE spaces are listed. Run `tpm_manager_client read_space` with the various indices and verify that the sizes and initial values of the spaces are correct. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 118 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55242/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Gerrit-Change-Number: 55242 Gerrit-PatchSet: 4 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot: Add support for ZTE spaces
by Aseda Aboagye (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Aaron Durbin. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55242 ) Change subject: security/vboot: Add support for ZTE spaces ...................................................................... Patch Set 3: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55242/comment/0b50f6f0_e2b9a3e9 PS2, Line 16: successfully. > Please document how to do that. Done Patchset: PS2: > Is successful create logged somehow? Successful create is not explicitly logged, however TPM factory initialization successful is logged when all spaces are created. File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/55242/comment/6efaf46f_268c7053 PS2, Line 194: * should be rare (interru pted initialization), so no big harm > Stray tab. Done https://review.coreboot.org/c/coreboot/+/55242/comment/4a397c24_f5ecbf31 PS2, Line 263: * Setup the Zero-Touch Enrollment(ZTE) related spaces. > Verb is spelled with a space: Set up. Done https://review.coreboot.org/c/coreboot/+/55242/comment/f738d331_d804c38c PS2, Line 288: VBDEBUG("%s: Failed to setup RMA + SN Bits space\n", __func__); > set up Done https://review.coreboot.org/c/coreboot/+/55242/comment/d62bb3f6_1c16c1bd PS2, Line 292: /* Setup Board ID */ > Set up […] Done https://review.coreboot.org/c/coreboot/+/55242/comment/0bba94be_99f0a5a7 PS2, Line 298: VBDEBUG("%s: Failed to setup Board ID space\n", __func__); > Set up (same below) Done https://review.coreboot.org/c/coreboot/+/55242/comment/2c5e0f00_829c5de2 PS2, Line 302: /* Setup RMA Bytes counter */ > Set up Done https://review.coreboot.org/c/coreboot/+/55242/comment/ae141d06_a5c22b94 PS2, Line 308: VBDEBUG("%s: Failed to define RMA Bytes space\n", __func__); > Use consistent wording (set up), and RMA Bytes Counter space. I'd prefer to keep this separate. "Set up" as used above implies that the space is defined and initialized. Whereas here, the space is only being defined. https://review.coreboot.org/c/coreboot/+/55242/comment/99cd35c7_effe69ad PS2, Line 352: * these are setup elsewhere via TPM vendor commands. > set up Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Gerrit-Change-Number: 55242 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 08:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
by Aseda Aboagye (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Christian Walter, Aaron Durbin. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55241 ) Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` ...................................................................... Patch Set 2: (1 comment) File src/security/tpm/tss/tcg-2.0/tss.c: https://review.coreboot.org/c/coreboot/+/55241/comment/0f45796b_d8e8341f PS1, Line 333: printk(BIOS_INFO, "%s: response is %x\n", > Should that be more debug level? Please paste some of these lines from your device to the commit me […] They probably ought to be debug level, but I was simply following the status quo. I've added some sample output to the commit message. If others feel strongly, perhaps we can fix the log level in a follow up CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/55241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 Gerrit-Change-Number: 55241 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 08:01:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add support for ZTE spaces
by Aseda Aboagye (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Andrey Pronin, Julius Werner, Aaron Durbin. Hello build bot (Jenkins), Andrey Pronin, Julius Werner, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55242 to look at the new patch set (#3). Change subject: security/vboot: Add support for ZTE spaces ...................................................................... security/vboot: Add support for ZTE spaces This commit adds support for the Chrome OS Zero-Touch Enrollment related spaces. For TPM 2.0 devices which don't use Cr50, coreboot will define the RMA+SN Bits, Board ID, and RMA Bytes counter spaces. The RMA+SN Bits space is 16 bytes initialized to all 0xFFs. The Board ID space is 12 bytes initialized to all 0xFFs. The RMA Bytes counter space is 8 bytes intialized to 0. BUG=b:184676425 BRANCH=None TEST=Build and flash lalala, verify that the ZTE spaces are created successfully by undefining the firmware antirollback space in the TPM such that the TPM undergoes factory initialization in coreboot. Reboot the DUT. Boot to CrOS and run `tpm_manager_client list_spaces` and verify that the ZTE spaces are listed. Run `tpm_manager_client read_space` with the various indices and verify that the sizes and initial values of the spaces are correct. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 118 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55242/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Gerrit-Change-Number: 55242 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2021