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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 )
Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
......................................................................
Patch Set 4:
(1 comment)
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/52585/comment/ee793ac2_5b9ab64b
PS4, Line 158: #define LB_MEM_SOFT_RESERVED 0xefffffff /* Special-purpose memory */
> But current lb_memory_range is not same as ACPI memory range address anyway? […]
It's not the same but by default the values are mapped 1:1. If you
don't want to have the same value in coreboot and e820. We could as
well use `7` here (or `17`; I don't know why there is a gap). And
let the code that fills the e820 table handle the mapping.
That's independent of the question if 0xefffffff is the right value
for e820 entries, though. What confuses me the most is that it is
the last value of the undefined range. So it seems unlikely that it
would become the official value later.
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Change subject: [WIP] src/superio/smsc: Add support for the SCH5555
......................................................................
Patch Set 3:
(1 comment)
File src/superio/smsc/sch5555/sch5555.h:
https://review.coreboot.org/c/coreboot/+/55250/comment/018d1b93_b24e49c0
PS1, Line 51: #define EMI_IOBASE 0xa00
: #define RUNTIME_IOBASE 0xa40
> My main concern is that mainboard code needs to enable LPC forwarding on these addresses. […]
Oh, another thing: I would prefix the macros in chip.h with `SCH5555_` to namespace them.
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Change subject: [WIP] src/superio/smsc: Add support for the SCH5555
......................................................................
Patch Set 3:
(1 comment)
File src/superio/smsc/sch5555/ramstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120875):
https://review.coreboot.org/c/coreboot/+/55250/comment/58498ccd_0ffdf4b7
PS3, Line 46: // BARs live in the LPC inteface LDN
'inteface' may be misspelled - perhaps 'interface'?
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Hello build bot (Jenkins), Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: [WIP] src/superio/smsc: Add support for the SCH5555
......................................................................
[WIP] src/superio/smsc: Add support for the SCH5555
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4
---
M src/superio/smsc/Makefile.inc
A src/superio/smsc/sch5555/Kconfig
A src/superio/smsc/sch5555/Makefile.inc
A src/superio/smsc/sch5555/bootblock.c
A src/superio/smsc/sch5555/emi.c
A src/superio/smsc/sch5555/ramstage.c
A src/superio/smsc/sch5555/sch5555.h
7 files changed, 356 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55250/3
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Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
......................................................................
soc/intel/alderlake: Correct TCSS XHCI Port status offset
The patch corrects TCSS XHCI Port status offset. The information is
captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619503).
BUG=None
TEST=Verified boot on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59
---
M src/soc/intel/alderlake/xhci.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/55230/3
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Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55251 )
Change subject: cpu/x86/lapic: Drop IOAPIC test
......................................................................
cpu/x86/lapic: Drop IOAPIC test
For the purpose of LAPIC IPI messaging it is not required to
evaluate if IOAPIC is enabled. The necessary enable_lapic()
will still be called as part of setup_lapic() within cpu init.
Change-Id: I8b6a34e39f755452f0af63ae0ced7279747c28fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/lapic/lapic_cpu_init.c
1 file changed, 5 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55251/1
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index ba88a36..589b8fa 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -506,18 +506,13 @@
/* Find the info struct for this CPU */
info = cpu_info();
- if (need_lapic_init()) {
- /* Ensure the local APIC is enabled */
+ /* Ensure the local APIC is enabled */
+ if (is_smp_boot())
enable_lapic();
- /* Get the device path of the boot CPU */
- cpu_path.type = DEVICE_PATH_APIC;
- cpu_path.apic.apic_id = lapicid();
- } else {
- /* Get the device path of the boot CPU */
- cpu_path.type = DEVICE_PATH_CPU;
- cpu_path.cpu.id = 0;
- }
+ /* Get the device path of the boot CPU */
+ cpu_path.type = DEVICE_PATH_APIC;
+ cpu_path.apic.apic_id = lapicid();
/* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
--
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE
......................................................................
cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE
Allows compile-time optimisation on platforms that do not wish
to enable runtime checking of X2APIC.
Legacy lapic_cpu_init() is incompatible so there is dependency
on PARALLEL_MP. Also stop_this_cpu() is incompatible, so there
is dependency on !AP_IN_SIPI_WAIT.
Since the code actually lacks enablement of X2APIC (apparently
assuming the blob has done it) and the other small flaws pointed
out in earlier reviews, X2APIC_RUNTIME is not selected per
default on any platform yet.
Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/Kconfig
M src/cpu/x86/lapic/lapic.c
M src/include/cpu/x86/lapic.h
3 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/55073/3
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 )
Change subject: [WIP] src/superio/smsc: Add support for the SCH5555
......................................................................
Patch Set 2:
(1 comment)
File src/superio/smsc/sch5555/sch5555.h:
https://review.coreboot.org/c/coreboot/+/55250/comment/4ae6b135_03b7dc77
PS1, Line 51: #define EMI_IOBASE 0xa00
: #define RUNTIME_IOBASE 0xa40
> Well it could be, I don't think it matters to the mainboard code what address these are mapped to as […]
My main concern is that mainboard code needs to enable LPC forwarding on these addresses. I guess we don't need to make them configurable for now (it would boil down to creating some Kconfig options), but I'd look into providing a way for a mainboard to know these values.
For example, I would #define these values in `chip.h` along with their size, and use the macros to program the `genX_dec` values in the devicetree:
superio/smsc/sch5555/chip.h:
#define EMI_IOBASE 0xa00
#define EMI_IOSIZE 0x40 /* TODO: placeholder, confirm */
#define RUNTIME_IOBASE 0xa40
#define RUNTIME_IOSIZE 0x40 /* TODO: placeholder, confirm */
mainboard/foo/bar/devicetree.cb:
register "gen1_dec" = "(EMI_IOSIZE - 1) << 16 | EMI_IOBASE | 1"
register "gen2_dec" = "(RUNTIME_IOSIZE - 1) << 16 | RUNTIME_IOBASE | 1"
If both I/O windows are contiguous, a single `genX_dec` register to cover both ranges would suffice.
The most straightforward way to determine the size of these I/O windows would be to derive them from vendor-programmed GENx_DEC values.
However, MMIO/PMIO windows almost always (I've yet to find an exception to this rule) need to be aligned to their size, and the BARs (base address registers) consequently have the lower address bits hardwired to 0. This allows software to check which bits "move", i.e. can be written to:
1. Write zeroes to the BAR.
2. Read back the BAR value.
3. Write ones to the BAR.
4. Read back the BAR value.
5. XOR the values from steps 2 and 4 to obtain a mask of the bits that move.
We have `pci_moving_configX` (X = 8, 16, 32) functions which do this with PCI registers. You could try to do this with the SCH5555 registers to double-check the values derived from GENx_DEC registers.
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Hello build bot (Jenkins), Felix Held,
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to look at the new patch set (#2).
Change subject: [WIP] src/superio/smsc: Add support for the SCH5555
......................................................................
[WIP] src/superio/smsc: Add support for the SCH5555
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4
---
M src/superio/smsc/Makefile.inc
A src/superio/smsc/sch5555/Kconfig
A src/superio/smsc/sch5555/Makefile.inc
A src/superio/smsc/sch5555/bootblock.c
A src/superio/smsc/sch5555/emi.c
A src/superio/smsc/sch5555/sch5555.h
6 files changed, 190 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55250/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55189 )
Change subject: cpu/x86/lapic: Redo DEBUG_HALT_SELF
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/x86/lapic/lapic_cpu_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120865):
https://review.coreboot.org/c/coreboot/+/55189/comment/615bc363_2081571c
PS3, Line 321: #define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0)
Single statement macros should not use a do {} while (0) loop
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