coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_SMP_INIT
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55204 to look at the new patch set (#4). Change subject: cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_SMP_INIT ...................................................................... cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_SMP_INIT It was not used, platforms should move away from LEGACY_SMP_INIT instead of maintaining this. Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c 1 file changed, 4 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/55204/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444 Gerrit-Change-Number: 55204 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
by Nico Huber (Code Review) 06 Jun '21

06 Jun '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports ...................................................................... mb/lenovo/t410: Enable WLAN and WUSB PCIe ports These PCH PCIe ports are used and should be enabled. Resolves: https://ticket.coreboot.org/issues/311 Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55169 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/lenovo/t410/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Swift Geek (Sebastian Grzywna): Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 4d10508..a4f3463 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -72,8 +72,8 @@ end device pci 1c.0 on end # PCIe Port #1: WWAN mPCIe slot - device pci 1c.1 off end # PCIe Port #2: WLAN mPCIe slot - device pci 1c.2 off end # PCIe Port #3: WUSB mPCIe slot + device pci 1c.1 on end # PCIe Port #2: WLAN mPCIe slot + device pci 1c.2 on end # PCIe Port #3: WUSB mPCIe slot device pci 1c.3 on end # PCIe Port #4: ExpressCard device pci 1c.4 on # PCIe Port #5: Ricoh SD & FireWire subsystemid 0x17aa 0x2133 -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/lenovo/t410: Update PCH PCIe RP comments
by Nico Huber (Code Review) 06 Jun '21

06 Jun '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55171 ) Change subject: mb/lenovo/t410: Update PCH PCIe RP comments ...................................................................... mb/lenovo/t410: Update PCH PCIe RP comments Looks like the comments were derived from a preproduction board's schematics. Production boards use a different port mapping. Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55171 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/lenovo/t410/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Swift Geek (Sebastian Grzywna): Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 5f167df..4d10508 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -71,11 +71,11 @@ subsystemid 0x17aa 0x215e end - device pci 1c.0 on end # PCIe Port #1 (wlan) - device pci 1c.1 off end # PCIe Port #2 (wwan) - device pci 1c.2 off end # PCIe Port #3 (wusb) - device pci 1c.3 on end # PCIe Port #4 (ExpressCard) - device pci 1c.4 on + device pci 1c.0 on end # PCIe Port #1: WWAN mPCIe slot + device pci 1c.1 off end # PCIe Port #2: WLAN mPCIe slot + device pci 1c.2 off end # PCIe Port #3: WUSB mPCIe slot + device pci 1c.3 on end # PCIe Port #4: ExpressCard + device pci 1c.4 on # PCIe Port #5: Ricoh SD & FireWire subsystemid 0x17aa 0x2133 chip drivers/ricoh/rce822 register "sdwppol" = "1" @@ -84,10 +84,10 @@ subsystemid 0x17aa 0x2134 end end - end # PCIe Port #5 (Ricoh SD & FW) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe) + end + device pci 1c.5 off end # PCIe Port #6: Intel GbE PHY (not PCIe) + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 -- To view, visit https://review.coreboot.org/c/coreboot/+/55171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Gerrit-Change-Number: 55171 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86: Default to PARALLEL_MP selected
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Damien Zammit, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Damien Zammit, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55196 to look at the new patch set (#5). Change subject: cpu/x86: Default to PARALLEL_MP selected ...................................................................... cpu/x86: Default to PARALLEL_MP selected Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/x86/Kconfig M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 30 files changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55196/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Gerrit-Change-Number: 55196 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Angel Pons (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Michael Niewöhner, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 1: (5 comments) File src/superio/smsc/sch5555/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55250/comment/b7b28c4c_f79a2334 PS1, Line 3: sch5555_ I'd drop the `sch5555_` prefix for .c files, they're in a folder named `sch5555`. https://review.coreboot.org/c/coreboot/+/55250/comment/28aa89c5_710321ed PS1, Line 4: sch5555_ramstage.c > does not exist -> remove Even better: add the file and uncomment the entry. File src/superio/smsc/sch5555/sch5555.h: https://review.coreboot.org/c/coreboot/+/55250/comment/d007ccca_d0e1b0e4 PS1, Line 82: uint8_t uart_no I would use the LDN or PNP device here, like other Super I/Os (ITE/Nuvoton/Winbond) do File src/superio/smsc/sch5555/sch5555_bootblock.c: https://review.coreboot.org/c/coreboot/+/55250/comment/a6d51a23_e1c9201c PS1, Line 2: > - no need to repeat the name in the filename […] early_init.c is usually for code compiled in both bootblock and romstage. https://review.coreboot.org/c/coreboot/+/55250/comment/a4848e36_b8f3f72c PS1, Line 15: smsc_write8(LDN_SELECT, LDN_GLOBAL); > I'd make a helper function for this: […] See Michael's comment -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:44:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Máté Kukri (mkukri) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Angel Pons, Felix Held. Máté Kukri (mkukri) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 1: (1 comment) File src/superio/smsc/sch5555/sch5555.h: https://review.coreboot.org/c/coreboot/+/55250/comment/d6b737c1_3da1c2d9 PS1, Line 51: #define EMI_IOBASE 0xa00 : #define RUNTIME_IOBASE 0xa40 > Aren't these mainboard-specific? Well it could be, I don't think it matters to the mainboard code what address these are mapped to as long as it knows where to write, but I can change it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:42:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Angel Pons (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 1: (10 comments) File src/superio/smsc/sch5555/sch5555.h: https://review.coreboot.org/c/coreboot/+/55250/comment/4b6c7a18_30238035 PS1, Line 8: #define SMSC_DATA 0x2f This could be different on another mainboard. https://review.coreboot.org/c/coreboot/+/55250/comment/818cbacd_0fee441d PS1, Line 51: #define EMI_IOBASE 0xa00 : #define RUNTIME_IOBASE 0xa40 Aren't these mainboard-specific? https://review.coreboot.org/c/coreboot/+/55250/comment/ccd69108_fa1d68a3 PS1, Line 60: uint8_t #include <types.h> File src/superio/smsc/sch5555/sch5555_bootblock.c: https://review.coreboot.org/c/coreboot/+/55250/comment/e61578dc_667b4a53 PS1, Line 15: smsc_write8(LDN_SELECT, LDN_GLOBAL); I'd make a helper function for this: void smsc_select_ldn(uint8_t ldn) { smsc_write8(LDN_SELECT, ldn); } https://review.coreboot.org/c/coreboot/+/55250/comment/d37a148d_4c237c27 PS1, Line 26: uint8_t #include <types.h> https://review.coreboot.org/c/coreboot/+/55250/comment/a39e9d34_95be6ce4 PS1, Line 45: smsc_write8(LDN_ACTIVE, 0x01); // Activate This and the `LDN_ACTIVE` macro should be dropped in favor of `pnp_set_enable()` from device/pnp_ops.h File src/superio/smsc/sch5555/sch5555_common.c: https://review.coreboot.org/c/coreboot/+/55250/comment/f0bf9d22_962c9c45 PS1, Line 20: uint8_t #include <types.h> https://review.coreboot.org/c/coreboot/+/55250/comment/94aead3b_ebb21b82 PS1, Line 22: outb(offset, SMSC_INDEX); : return inb(SMSC_DATA); Seems like you could use `pnp_read_config()` from device/pnp_ops.h https://review.coreboot.org/c/coreboot/+/55250/comment/8dece12e_da9ff2f2 PS1, Line 37: val |= smsc_read8(offset); : val |= smsc_read8(offset + 1) << 8; : val |= smsc_read8(offset + 2) << 16; : val |= smsc_read8(offset + 3) << 24; How about: val |= smsc_read16(offset); val |= smsc_read16(offset + 2) << 16; Similar story for writes https://review.coreboot.org/c/coreboot/+/55250/comment/b8cd6eb9_e596d9c7 PS1, Line 46: outb(offset, SMSC_INDEX); : outb(value, SMSC_DATA); Seems like you could use `pnp_write_config()` from device/pnp_ops.h -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:39:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/haswell/gma.c: Add Desktop HD 4400 id
by Michael Niewöhner (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55243 ) Change subject: northbridge/haswell/gma.c: Add Desktop HD 4400 id ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7c38206b1ddfe486298cd3921fcb762a89ec51 Gerrit-Change-Number: 55243 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:37:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Michael Niewöhner (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 1: (11 comments) File src/superio/smsc/sch5555/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55250/comment/498bba9d_fac235d9 PS1, Line 4: sch5555_ramstage.c does not exist -> remove File src/superio/smsc/sch5555/sch5555_bootblock.c: https://review.coreboot.org/c/coreboot/+/55250/comment/50101d17_b99db070 PS1, Line 2: - no need to repeat the name in the filename - usually this file would be called early_init.c https://review.coreboot.org/c/coreboot/+/55250/comment/c02345fc_3e34ef25 PS1, Line 12: smsc_conf_enter(); pnp_enter_conf_state; look at src/superio/smsc/sch5545/sch5545_early_init.c for an example https://review.coreboot.org/c/coreboot/+/55250/comment/5c74117a_817f45ef PS1, Line 15: smsc_write8(LDN_SELECT, LDN_GLOBAL); use pnp_set_logical_device https://review.coreboot.org/c/coreboot/+/55250/comment/24e8fbf5_f85a31e5 PS1, Line 19: smsc_write8(LDN_SELECT, LDN_LPCI); as above https://review.coreboot.org/c/coreboot/+/55250/comment/21672dbe_22982f6f PS1, Line 23: smsc_conf_exit pnp_exit_conf_mode https://review.coreboot.org/c/coreboot/+/55250/comment/b0f4eb0b_ed8408d5 PS1, Line 31: smsc_write8(LDN_SELECT, LDN_LPCI); : : switch (uart_no) { : case SCH5555_UART1: : smsc_write32(LPCI_UART1_BAR, serial_iobase << 16 | 0x8707); : smsc_write8(LDN_SELECT, LDN_UART1); : break; : case SCH5555_UART2: : smsc_write32(LPCI_UART2_BAR, serial_iobase << 16 | 0x8707); : smsc_write8(LDN_SELECT, LDN_UART2); : break; : } : : // Setup UART's configuration registers : smsc_write8(LDN_ACTIVE, 0x01); // Activate : smsc_write8(0x0f, 0x02); // Config select you could avoid this by letting the board pass the dev instead of just the uart_no. have a look at src/superio/aspeed/common/early_serial.c and src/mainboard/ocp/deltalake/bootblock.c for an example https://review.coreboot.org/c/coreboot/+/55250/comment/9225791e_64ed5cfe PS1, Line 48: smsc_conf_exit as above File src/superio/smsc/sch5555/sch5555_common.c: https://review.coreboot.org/c/coreboot/+/55250/comment/442abe01_8f5af392 PS1, Line 6: // : // Super I/O register access : // nit: We usually use C89 style (C99 is allowed, though) ``` /* Super I/O register access */ ``` or ``` /* * Super I/O register access */ ``` https://review.coreboot.org/c/coreboot/+/55250/comment/69aa5135_9a81f27a PS1, Line 10: oid smsc_conf_enter(void) : { : outb(0x55, SMSC_INDEX); : } : : void smsc_conf_exit(void) : { : outb(0xaa, SMSC_INDEX); : } not sio-specific,make use of pnp_enter_conf_mode, pnp_exit_conf_mode instead (see src/superio/common,src/device/pnp_device.c) https://review.coreboot.org/c/coreboot/+/55250/comment/8c5f8d8c_516bfe03 PS1, Line 52: sc_write8(offset, value & 0xff); : smsc_writ unsure, but might outw work? -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:32:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: FSP2.0 platforms: Use bootloader reserved memory for BERT
by Nico Huber (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55142 ) Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I'm a little late to the BERT topic. I don't understand the reasons to put it outside CBMEM, it seems rather odd and a workaround to other issues (even bugs if the OS sees type 16 e820 entries, cf. CB:45391). Can somebody shed some light on it? -- To view, visit https://review.coreboot.org/c/coreboot/+/55142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 Gerrit-Change-Number: 55142 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 13:31:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2021