coreboot-gerrit June 2021

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Change in coreboot[master]: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon
by build bot (Jenkins) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55254 ) Change subject: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/alderlake/romstage/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/d5a1f66b_abc33a02 PS1, Line 147: if(cse_get_rw_rdev(&desc_dev) < 0) space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/ecaf8a43_a0338103 PS1, Line 155: if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x44 ) { space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/ae3224fc_d86a7c11 PS1, Line 204: * if CSE RW blob's version is different from CSE RW version. code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/55254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Gerrit-Change-Number: 55254 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 17:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon
by Sridhar Siricilla (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55254 ) Change subject: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon ...................................................................... soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon The patch corrects PMC Descriptpr 7 which is part of Descriptor Region if system having Alderlake B silicon TEST=Verified PMC Descriptor 7 getting modified for Alderlake B silicon Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55254/1 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index e6a9592..c0c8732 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -12,8 +12,15 @@ #include <soc/intel/common/smbios.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <soc/intel/common/reset.h> +#include <fmap.h> +#include <commonlib/region.h> +#include <intelblocks/mp_init.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -22,6 +29,14 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +#define SI_DESC_REGION "SI_DESC" +#define SI_DESC_REGION_SZ 4096 +#define PMC_DESC_7_BYTE3 0xc32 + +#define DESC_REGION_CONFIG_FAIL -1 +#define GLOBAL_RESET_REQUIRED 1 +#define GLOBAL_RESET_IS_NOT_REQUIRED 2 + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -114,6 +129,45 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } +static int8_t cse_get_rw_rdev(struct region_device *rdev) +{ + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return -1; + } + + return 0; +} + +static uint8_t configure_cpu_boot_fivr(void) +{ + uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + struct region_device desc_dev; + + if(cse_get_rw_rdev(&desc_dev) < 0) + return DESC_REGION_CONFIG_FAIL; + + if (rdev_readat(&desc_dev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return DESC_REGION_CONFIG_FAIL; + } + + if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x44 ) { + si_desc_buf[PMC_DESC_7_BYTE3] = 0x40; + + if (rdev_writeat(&desc_dev, si_desc_buf, 0, SI_DESC_REGION_SZ) + != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update CPU BOOT FIVR strap in the Descriptor Region\n"); + return DESC_REGION_CONFIG_FAIL; + } + printk(BIOS_DEBUG, "Update of CPU BOOT FIVR strap successful, trigger GLOBAL RESET\n"); + return GLOBAL_RESET_REQUIRED; + } + + printk(BIOS_DEBUG, "CPU BOOT FIVR configuration is not required!\n"); + return GLOBAL_RESET_IS_NOT_REQUIRED; +} + void mainboard_romstage_entry(void) { bool s3wake; @@ -129,18 +183,36 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); + if (!s3wake) { + uint32_t cpu_id = cpu_get_cpuid(); + int8_t ret = GLOBAL_RESET_IS_NOT_REQUIRED; + + /* + * If configure_cpu_boot_fivr() requests GLOBAL_RESET,let's do after + * cse_fw_sync(). + */ + if (cpu_id == CPUID_ALDERLAKE_B0) + ret = configure_cpu_boot_fivr(); + /* * cse_fw_sync() must be called after DRAM initialization as * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) * is expected to be executed after DRAM initialization. * When AP starts from G3, cse_fw_sync() triggers GLOBAL RESET after * marking CSE's next boot partition to RW. Also, it trigger CSE Firmware update - * if CSE RW blob's version is different from CSE RW version. + * if CSE RW blob's version is different from CSE RW version. */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) cse_fw_sync(); + /* + * if configure_cpu_boot_fivr() requests GLOBAL RESET and cse_fw_sync() didn't + * trigger GLOBAL RESET, so trigger GLOBAL RESET here + */ + if (ret == GLOBAL_RESET_REQUIRED) + do_global_reset(); + save_dimm_info(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/55254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Gerrit-Change-Number: 55254 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add inline comment to cse_fw_sync()
by Sridhar Siricilla (Code Review) 06 Jun '21

06 Jun '21

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Change in coreboot[master]: soc/intel/{common,alderlake}: Define Alderlake Platform for ADL-P/M
by Sridhar Siricilla (Code Review) 06 Jun '21

06 Jun '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55252 ) Change subject: soc/intel/{common,alderlake}: Define Alderlake Platform for ADL-P/M ...................................................................... soc/intel/{common,alderlake}: Define Alderlake Platform for ADL-P/M The patch defines "Alderlake Platform" for Alderlake-P and Alderlake-M silicon variants. Hence, rename all ADL-P SI CPUID macros as Alderlake A0/B0/C0. TEST=Verify boot on Brya. After change, relevent coreboot logs appear as below: CPU: ID 906a1, Alderlake Platform, ucode: 00000119 CPU: AES supported, TXT supported, VT supported MCH: device id 4601 (rev 03) is Alderlake-P PCH: device id 5181 (rev 00) is Alderlake-P SKU IGD: device id 46b0 (rev 04) is Alderlake P GT2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15 --- M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/55252/1 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 15391ab..d0f82b7 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -22,9 +22,9 @@ u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, - { CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" }, - { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" }, + { CPUID_ALDERLAKE_A0, "Alderlake Platform" }, + { CPUID_ALDERLAKE_B0, "Alderlake Platform" }, + { CPUID_ALDERLAKE_C0, "Alderlake Platform" }, }; static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7e8c199..9f55f46 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -67,9 +67,9 @@ { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_B0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_C0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3d8290f..23a2037 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -45,9 +45,9 @@ #define CPUID_ELKHARTLAKE_A0 0x90660 #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_P_A0 0x906a0 -#define CPUID_ALDERLAKE_P_B0 0x906a2 -#define CPUID_ALDERLAKE_M_A0 0x906a1 +#define CPUID_ALDERLAKE_A0 0x906a0 +#define CPUID_ALDERLAKE_B0 0x906a1 +#define CPUID_ALDERLAKE_C0 0x906a2 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. -- To view, visit https://review.coreboot.org/c/coreboot/+/55252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15 Gerrit-Change-Number: 55252 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/haswell/gma.c: Add Desktop HD 4400 id
by Angel Pons (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55243 ) Change subject: northbridge/haswell/gma.c: Add Desktop HD 4400 id ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/northbridge/intel/haswell/gma.c: https://review.coreboot.org/c/coreboot/+/55243/comment/5425a59c_fba1cf70 PS1, Line 476: Desktop GT2 (HD 4400) Meh, I just checked: this is `Dev2-HSW GT1.5 Desktop`. -- To view, visit https://review.coreboot.org/c/coreboot/+/55243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7c38206b1ddfe486298cd3921fcb762a89ec51 Gerrit-Change-Number: 55243 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 17:07:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Máté Kukri (mkukri) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Angel Pons, Michael Niewöhner, Felix Held. Máté Kukri (mkukri) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 4: (1 comment) File src/superio/smsc/sch5555/ramstage.c: https://review.coreboot.org/c/coreboot/+/55250/comment/cbdb3040_d7f9603c PS4, Line 54: uint8_t tmp = pnp_read_config(lpci, bar + 1); : pnp_write_config(lpci, bar + 1, tmp | 0x80); > How about: […] That's only defined in simple device "mode". -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 17:04:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Angel Pons (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Michael Niewöhner, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 4: (13 comments) File src/superio/smsc/sch5555/ramstage.c: https://review.coreboot.org/c/coreboot/+/55250/comment/0818a4c7_9e266e57 PS4, Line 4: #include <device/pnp.h> : #include <console/console.h> nit: I'd swap these two includes for the sake of alphabetical ordering https://review.coreboot.org/c/coreboot/+/55250/comment/919403a9_a2100637 PS4, Line 46: struct device *lpci = dev_find_slot_pnp(dev->path.pnp.port, SCH5555_LDN_LPCI); : if (!lpci) { : printk(BIOS_ERR, "SCH5555 LPC interface not present in device tree!\n"); : return; : } I would do this once in `sch5555_set_resources()` and pass around the `lpci` device pointer as parameter. This avoids repeating the code and the error message in logs. https://review.coreboot.org/c/coreboot/+/55250/comment/a8b52c34_5b7817ef PS4, Line 53: uint8_t bar nit: could be const. Also, shouldn't we avoid trying to assign a BAR if `ldn_to_bar()` returns 0? https://review.coreboot.org/c/coreboot/+/55250/comment/ad9e1cb7_7245fd0a PS4, Line 54: uint8_t tmp = pnp_read_config(lpci, bar + 1); : pnp_write_config(lpci, bar + 1, tmp | 0x80); How about: pnp_unset_and_set_config(lpci, bar + 1, 0, 1 << 7); https://review.coreboot.org/c/coreboot/+/55250/comment/2fe4daab_8d313a5d PS4, Line 59: pnp_set_logical_device(dev); Any reason to do this? Same for IRQ/DRQ https://review.coreboot.org/c/coreboot/+/55250/comment/1a77ce8c_f20765e3 PS4, Line 72: pnp_write_config(dev, index, irq); I would add a `pnp_set_logical_device(dev);` call before this write. https://review.coreboot.org/c/coreboot/+/55250/comment/bb898da7_07985ad3 PS4, Line 85: pnp_write_config(lpci, SCH5555_LPCI_IRQ_CONF + irq, dev->path.pnp.device); I'd parametrise the `SCH5555_LPCI_IRQ_CONF` macro: #define SCH5555_LPCI_IRQ_CONF(irq) (0x40 + (irq)) The parentheses are necessary to avoid operation order problems. https://review.coreboot.org/c/coreboot/+/55250/comment/312b9055_be40591f PS4, Line 107: SCH5555_LPCI_DMA_CONF + drq * 2 I'd parametrise the `SCH5555_LPCI_DMA_CONF` macro: #define SCH5555_LPCI_DMA_CONF(drq) (0x50 + (drq) * 2) The parentheses are necessary to avoid operation order problems. https://review.coreboot.org/c/coreboot/+/55250/comment/f53d7597_40806307 PS4, Line 107: dev I'd use `lpci` instead of `dev` here. https://review.coreboot.org/c/coreboot/+/55250/comment/1189f757_0504eedf PS4, Line 152: SCH5555_LDN_PARPORT How about `SCH5555_LDN_PP` instead? It's shorter and consistent with SCH5545 File src/superio/smsc/sch5555/sch5555.h: https://review.coreboot.org/c/coreboot/+/55250/comment/3a49d43f_889d231f PS4, Line 9: #define SCH5555_LDN_SELECT 0x07 Is this needed? https://review.coreboot.org/c/coreboot/+/55250/comment/bd7b2263_78c7463b PS4, Line 26: #define SCH5555_LDN_ACTIVE 0x30 Is this needed? https://review.coreboot.org/c/coreboot/+/55250/comment/ab1b5750_68eb98c1 PS4, Line 46: the datasheet "the SCH5627P datasheet" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 16:48:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by build bot (Jenkins) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Michael Niewöhner, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 4: (2 comments) File src/superio/smsc/sch5555/ramstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120877): https://review.coreboot.org/c/coreboot/+/55250/comment/7854b456_1b8eaea7 PS4, Line 88: pnp_write_config(lpci, SCH5555_LPCI_IRQ_CONF + irq, dev->path.pnp.device | 0x80); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120877): https://review.coreboot.org/c/coreboot/+/55250/comment/7d5fbb99_777d2c28 PS4, Line 152: { NULL, SCH5555_LDN_PARPORT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1, 0x0ff8 }, line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 16:40:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Máté Kukri (mkukri) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Michael Niewöhner, Felix Held. Hello build bot (Jenkins), Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55250 to look at the new patch set (#4). Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... [WIP] src/superio/smsc: Add support for the SCH5555 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 --- M src/superio/smsc/Makefile.inc A src/superio/smsc/sch5555/Kconfig A src/superio/smsc/sch5555/Makefile.inc A src/superio/smsc/sch5555/bootblock.c A src/superio/smsc/sch5555/emi.c A src/superio/smsc/sch5555/ramstage.c A src/superio/smsc/sch5555/sch5555.h 7 files changed, 356 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55250/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset
by Sridhar Siricilla (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 ) Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55230/comment/1eeb9a08_14f7e773 PS2, Line 10: 619502 > 619503 Ack File src/soc/intel/alderlake/xhci.c: https://review.coreboot.org/c/coreboot/+/55230/comment/4603265b_afddf74e PS1, Line 19: 10 > You're right, should be 0 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Gerrit-Change-Number: 55230 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 06 Jun 2021 16:08:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021