coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Máté Kukri (mkukri) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Angel Pons, Felix Held. Hello build bot (Jenkins), Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55250 to look at the new patch set (#5). Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... [WIP] src/superio/smsc: Add support for the SCH5555 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 --- M src/superio/smsc/Makefile.inc A src/superio/smsc/sch5555/Kconfig A src/superio/smsc/sch5555/Makefile.inc A src/superio/smsc/sch5555/bootblock.c A src/superio/smsc/sch5555/emi.c A src/superio/smsc/sch5555/ramstage.c A src/superio/smsc/sch5555/sch5555.h 7 files changed, 338 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55250/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 5 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] src/superio/smsc: Add support for the SCH5555
by Michael Niewöhner (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Máté Kukri (mkukri), Angel Pons, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55250 ) Change subject: [WIP] src/superio/smsc: Add support for the SCH5555 ...................................................................... Patch Set 4: (5 comments) File src/superio/smsc/sch5555/ramstage.c: https://review.coreboot.org/c/coreboot/+/55250/comment/63bf85e3_9b5ea238 PS4, Line 145: PNP_MSC0 | PNP_MSC1 same as below https://review.coreboot.org/c/coreboot/+/55250/comment/706d6cd9_7a36331a PS4, Line 149: PNP_MSC0 is it mandatory to configure this register? if not, drop this for the same reason as below https://review.coreboot.org/c/coreboot/+/55250/comment/d433aa63_e1ca2e40 PS4, Line 150: PNP_MSC0 | PNP_MSC1 | : PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 drop them, since they are not required. else, coreboot will complain when they are not set in the devicetree https://review.coreboot.org/c/coreboot/+/55250/comment/52ac6d01_b03d725e PS4, Line 152: PNP_MSC0 | PNP_MSC1 see above and check File src/superio/smsc/sch5555/sch5555_bootblock.c: https://review.coreboot.org/c/coreboot/+/55250/comment/257925dc_deeedd91 PS1, Line 2: > early_init.c is usually for code compiled in both bootblock and romstage. both are "early" ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/55250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Gerrit-Change-Number: 55250 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri (mkukri) <kukri.mate(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 19:54:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Separate stop_this_cpu()
by build bot (Jenkins) (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55193 ) Change subject: cpu/x86/lapic: Separate stop_this_cpu() ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/lapic/lapic_cpu_stop.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120900): https://review.coreboot.org/c/coreboot/+/55193/comment/b6559eb2_336e9b87 PS3, Line 22: #define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0) Single statement macros should not use a do {} while (0) loop -- To view, visit https://review.coreboot.org/c/coreboot/+/55193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Gerrit-Change-Number: 55193 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 19:51:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Do not inline some utility functions
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55258 ) Change subject: cpu/x86/lapic: Do not inline some utility functions ...................................................................... cpu/x86/lapic: Do not inline some utility functions Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 3 files changed, 45 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/55258/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index ea16014..8e89d29 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c @@ -10,3 +9,9 @@ romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c + +bootblock-y += lapic.c +verstage_x86-y += lapic.c +romstage-y += lapic.c +ramstage-y += lapic.c +postcar-y += lapic.c diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 468a5dc..9f3cff5 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -1,10 +1,37 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/lapic.h> +#include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> #include <console/console.h> #include <stdint.h> -void lapic_virtual_wire_mode_init(void) +void enable_lapic(void) +{ + msr_t msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.hi &= 0xffffff00; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; + msr.lo |= LAPIC_BASE_MSR_ENABLE; + wrmsr(LAPIC_BASE_MSR, msr); +} + +void disable_lapic(void) +{ + msr_t msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.lo &= ~LAPIC_BASE_MSR_ENABLE; + wrmsr(LAPIC_BASE_MSR, msr); +} + +/* See if I need to initialize the local APIC */ +static int need_lapic_init(void) +{ + return CONFIG(SMP) || CONFIG(IOAPIC); +} + +static void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... @@ -40,3 +67,11 @@ printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid()); printk(BIOS_INFO, "done.\n"); } + +void setup_lapic(void) +{ + if (need_lapic_init()) + lapic_virtual_wire_mode_init(); + else + disable_lapic(); +} diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index cf048a8..a3d0fcb 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -116,25 +116,6 @@ do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); } -static inline void enable_lapic(void) -{ - msr_t msr; - msr = rdmsr(LAPIC_BASE_MSR); - msr.hi &= 0xffffff00; - msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; - msr.lo |= LAPIC_DEFAULT_BASE; - msr.lo |= LAPIC_BASE_MSR_ENABLE; - wrmsr(LAPIC_BASE_MSR, msr); -} - -static inline void disable_lapic(void) -{ - msr_t msr; - msr = rdmsr(LAPIC_BASE_MSR); - msr.lo &= ~LAPIC_BASE_MSR_ENABLE; - wrmsr(LAPIC_BASE_MSR, msr); -} - static __always_inline unsigned int initial_lapicid(void) { uint32_t lapicid; @@ -168,20 +149,8 @@ void stop_this_cpu(void); #endif -void lapic_virtual_wire_mode_init(void); - -/* See if I need to initialize the local APIC */ -static inline int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static inline void setup_lapic(void) -{ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); - else - disable_lapic(); -} +void enable_lapic(void); +void disable_lapic(void); +void setup_lapic(void); #endif /* CPU_X86_LAPIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Gerrit-Change-Number: 55258 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Marshall Dawson, Arthur Heymans, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55194 to look at the new patch set (#3). Change subject: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references ...................................................................... cpu/x86/lapic: Replace LOCAL_APIC_ADDR references Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/smp/mpspec.h M src/arch/x86/mpspec.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/smm/smmhandler.S M src/include/cpu/x86/lapic_def.h M src/mainboard/apple/macbook21/mptable.c M src/mainboard/asus/a88xm-e/mptable.c M src/mainboard/asus/p2b/variants/p2b-d/mptable.c M src/mainboard/asus/p2b/variants/p2b-ds/mptable.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/getac/p470/mptable.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/roda/rk886ex/mptable.c M src/soc/amd/cezanne/data_fabric.c M src/soc/amd/picasso/data_fabric.c M src/soc/amd/stoneyridge/northbridge.c 21 files changed, 29 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/55194/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Gerrit-Change-Number: 55194 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/lapic: Separate stop_this_cpu()
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55193 to look at the new patch set (#3). Change subject: cpu/x86/lapic: Separate stop_this_cpu() ...................................................................... cpu/x86/lapic: Separate stop_this_cpu() Function is needed with PARALLEL_MP and excluding guard will be added to the source file. The incompatibilities with X2APIC_SUPPORT have been fixed so the exclusion is removed here too. Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/lapic_cpu_init.c A src/cpu/x86/lapic/lapic_cpu_stop.c M src/include/cpu/x86/lapic.h 5 files changed, 75 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/55193/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Gerrit-Change-Number: 55193 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/amd/hudson: Skip setting up LPC decode for base < 0x20
by Paul Menzel (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54669 ) Change subject: sb/amd/hudson: Skip setting up LPC decode for base < 0x20 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Could this please be discussed on the mailing list? i started the thread *IO resources with base == 0/LPC decode* [1]. [1]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/SD3L… -- To view, visit https://review.coreboot.org/c/coreboot/+/54669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idec3832d8d1ab95ae9747ce87792ee7b474540c7 Gerrit-Change-Number: 54669 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Jun 2021 19:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] arch/x86/ioapic: Drop irq_on_fsb as a configurable item
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Stefan Ott, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Alexander Couzens, Patrick Rudolph. Hello Stefan Ott, build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55257 to look at the new patch set (#2). Change subject: [WIP] arch/x86/ioapic: Drop irq_on_fsb as a configurable item ...................................................................... [WIP] arch/x86/ioapic: Drop irq_on_fsb as a configurable item APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/drivers/generic/ioapic/chip.h M src/drivers/generic/ioapic/ioapic.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 13 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/55257/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Gerrit-Change-Number: 55257 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/generic/ioapic: Use arch/x86/ioapic
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55185 ) Change subject: drivers/generic/ioapic: Use arch/x86/ioapic ...................................................................... Patch Set 4: (1 comment) File src/drivers/generic/ioapic/ioapic.c: https://review.coreboot.org/c/coreboot/+/55185/comment/da7b3a60_c491a418 PS3, Line 17: config->enable_virtual_wire); > The only boards that set `irq_on_fsb` are gm45 boards and samsung/lumpy. […] Which is all the boards that do have drivers/generic/ioapic? Let's move discussion to CB:55257. -- To view, visit https://review.coreboot.org/c/coreboot/+/55185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f Gerrit-Change-Number: 55185 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Jun 2021 19:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/ioapic: Drop irq_on_fsb as a configurable item
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55257 ) Change subject: arch/x86/ioapic: Drop irq_on_fsb as a configurable item ...................................................................... arch/x86/ioapic: Drop irq_on_fsb as a configurable item APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/drivers/generic/ioapic/chip.h M src/drivers/generic/ioapic/ioapic.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 12 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/55257/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a488b55..6a25dae 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -172,14 +172,6 @@ default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config IOAPIC_INTERRUPTS_ON_FSB - bool - default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - -config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - bool - default n - config HPET_ADDRESS_OVERRIDE def_bool n diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index bdbcfbf..9c20cae 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -32,8 +32,7 @@ void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base); -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire); +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire); #endif #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index c148534..d57408a 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -109,13 +109,8 @@ } -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire) +void ioapic_set_boot_config(bool irq_on_fsb) { - int first = 0, last; - - set_ioapic_id(ioapic_base, ioapic_id); - if (irq_on_fsb) { /* * For the Pentium 4 and above APICs deliver their interrupts @@ -129,6 +124,13 @@ "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); } +} + +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire) +{ + int first = 0, last; + + set_ioapic_id(ioapic_base, ioapic_id); if (enable_virtual_wire) { route_i8259_irq0(ioapic_base); @@ -142,6 +144,5 @@ void setup_ioapic(void *ioapic_base, u8 ioapic_id) { - setup_ioapic_helper(ioapic_base, ioapic_id, - CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true); + setup_ioapic_helper(ioapic_base, ioapic_id, true); } diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index 88720bb..9a9395f 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -6,7 +6,6 @@ typedef struct drivers_generic_ioapic_config { u32 version; u8 apicid; - u8 irq_on_fsb; u8 enable_virtual_wire; u8 have_isa_interrupts; void *base; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 708d9a1..4a8bcf8 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -13,8 +13,7 @@ if (!dev->enabled || !config) return; - setup_ioapic_helper(config->base, config->apicid, config->irq_on_fsb, - config->enable_virtual_wire); + setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire); } static void ioapic_read_resources(struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 537841e..c3b6ea6 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -4,7 +4,6 @@ def_bool y select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX - select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 5886aff..ae389de 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -143,7 +143,6 @@ chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 80288bf..4db554b 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -133,7 +133,6 @@ chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 3965053..0af9837 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -121,7 +121,6 @@ device pci 1f.0 on # LPC bridge chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 85d140c..17d506b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -109,7 +109,6 @@ chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 4 on end diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index e32ae36..fafacc1 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -42,12 +42,6 @@ reg32 |= 0x00270000; io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 4950940..1b6936e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -290,12 +290,6 @@ reg32 |= (redir_entries - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 65be16e..a099c31 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -42,12 +42,6 @@ reg32 |= (PCH_LP_REDIR_ETR - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } /* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c6b42ea..caac1b8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -48,12 +48,6 @@ /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index f6c04a5..6ff6064 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -50,11 +50,7 @@ set_ioapic_id(VIO_APIC_VADDR, 0x02); - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); + ioapic_set_boot_config(VIO_APIC_VADDR, true); } static void i82801dx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9eabf02..ababe67 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,12 +34,6 @@ static void i82801gx_enable_ioapic(struct device *dev) { set_ioapic_id(VIO_APIC_VADDR, 0x02); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 6092347..8cc9b42 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -40,12 +40,6 @@ /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fb42145..01fff14 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -49,12 +49,6 @@ reg32 |= 0x00270000; } io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/55257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Gerrit-Change-Number: 55257 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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