coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Update DPTF parameters
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55208 ) Change subject: mb/google/dedede/var/sasukette: Update DPTF parameters ...................................................................... mb/google/dedede/var/sasukette: Update DPTF parameters Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Id18a38cddbcacbafbe2c54d94dbda5e00de02b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Evan Green <evgreen(a)chromium.org> --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Evan Green: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Tao Xia: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 0f48365..16bf546 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -74,7 +74,42 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Camera + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "10" # TCC of 95C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 52, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 54, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 5000),}" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),}" + register "controls.power_limits.pl1" = "{ + .min_power = 5000, + .max_power = 7000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 250,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/55208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a38cddbcacbafbe2c54d94dbda5e00de02b3b Gerrit-Change-Number: 55208 Gerrit-PatchSet: 2 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rui Huang <huangrui(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: bd82x6x boards: Drop redundant `c2_latency`
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55212 ) Change subject: bd82x6x boards: Drop redundant `c2_latency` ...................................................................... bd82x6x boards: Drop redundant `c2_latency` If unspecified, chipset code already uses 101, and 0x65 == 101. Change-Id: I524ca492fa577003df23017756f74a455582132f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8z77-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/optiplex_9010/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 31 files changed, 0 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 3689926..8f7573a 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -25,7 +25,6 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index eb0c944..83b6597 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -33,7 +33,6 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 07c0a86..32f0cd4 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 5860556..ca09d2f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -19,7 +19,6 @@ device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x - register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asus/p8z77-series/devicetree.cb b/src/mainboard/asus/p8z77-series/devicetree.cb index 1b9d14d..9710118 100644 --- a/src/mainboard/asus/p8z77-series/devicetree.cb +++ b/src/mainboard/asus/p8z77-series/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 9dc6a7c..35c3ae3 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -18,7 +18,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 536eef7..b3b1a1c 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -31,7 +31,6 @@ subsystemid 0x8086 0x7270 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x0000164d" register "gen2_dec" = "0x000c0681" diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index c85f2e4..ec585b9 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -24,7 +24,6 @@ register "alt_gp_smi_en" = "0x0004" register "gpi2_routing" = "1" register "gpi12_routing" = "2" - register "c2_latency" = "0x0065" register "gen1_dec" = "0x007c0a01" register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 8816f10..7ca9a8b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -31,7 +31,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "c2_latency" = "0x0065" device pci 14.0 on # USB 3.0 Controller subsystemid 0x1458 0x5007 diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 479d813..3f07202 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -18,7 +18,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 7cdb8a3..9dee30f 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -60,8 +60,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 0d83267..76d04d6 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -24,7 +24,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 7fc936d..3dd8825 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -29,7 +29,6 @@ device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH - register "c2_latency" = "0x0065" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 0aca0a6..5204e60 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -24,7 +24,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 7 PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index c554b6c..389b44e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -28,7 +28,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "sata_port_map" = "0x1" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 950d68a..a878019 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -34,8 +34,6 @@ # Disable root port coalescing register "pcie_port_coalesce" = "0" - register "c2_latency" = "101" # c2 not supported - register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 4655baa..86205f8 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -30,7 +30,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index fbf54d4..3c1fc9e 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -28,7 +28,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 3ba3a2d..e42e519 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index cfe8929..ab98ca0 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -59,8 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 950e83d..112dfe7 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -28,7 +28,6 @@ subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 7f95170..75a65f9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -59,7 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 40b005d..a1e24d5 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b179f4f..ffa0b93 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -53,7 +53,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index dc9e037..abe40b1 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -56,7 +56,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "0x0065" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 2707197..30260b0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -58,7 +58,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index a41cfea..53eb23a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a774d84..1f81311 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -59,7 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 083c427..6c97e1f 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 35c77aa..876f920 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -12,7 +12,6 @@ end device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" register "pcie_port_coalesce" = "1" diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 13b2043..49fcff5 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 off end # iGPU device pci 06.0 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) -- To view, visit https://review.coreboot.org/c/coreboot/+/55212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I524ca492fa577003df23017756f74a455582132f Gerrit-Change-Number: 55212 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55012 ) Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/i82371eb/fadt.c: https://review.coreboot.org/c/coreboot/+/55012/comment/7ecdb179_31a7452f PS2, Line 45: /* not supported */ > The PIIX4 datasheet doesn't mention anything about centuries nor centenary (I looked for "cent"). […] This is not a special feature of the chipset. It is more a random byte inside the CMOS RAM which is used to store the century. Our MC146818 RTC driver just uses this location to store this information and the OS (at least Linux) can be mada aware of this by reporting this location via FADT. -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Jun 2021 04:51:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: add support for clock driver
by Ravi Kumar Bokka (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, Paul Menzel, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50580 ) Change subject: sc7280: add support for clock driver ...................................................................... Patch Set 40: (1 comment) Patchset: PS26: > As mentioned in the meeting, I think that this looks like it was mostly copied from trogdor. […] As discussed with clock team POC in the meeting on May19th, clock driver needs to be picked up as it is, we would cleanup later when we have a common clock driver in July. -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 04:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/w541: Add Thinkpad W541
by amersel (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Peter Lemenkov, Alexander Couzens, Patrick Rudolph. amersel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52659 ) Change subject: mb/lenovo/w541: Add Thinkpad W541 ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: Patchset 14 enables the M.2 SATA slot by updating the sata port map in the devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/52659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Gerrit-Change-Number: 52659 Gerrit-PatchSet: 14 Gerrit-Owner: amersel Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 03:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/w541: Add Thinkpad W541
by amersel (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Peter Lemenkov, Alexander Couzens, Patrick Rudolph. Hello build bot (Jenkins), Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52659 to look at the new patch set (#14). Change subject: mb/lenovo/w541: Add Thinkpad W541 ...................................................................... mb/lenovo/w541: Add Thinkpad W541 Adds support for the Thinkpad W541 based on Peter Lemenkov's initial W541 port. Compiled and tested with SeaBIOS booting into Arch Linux 5.10.32-lts using a VGA BIOS ROM extracted using VBiosFinder. The Haswell mrc.bin blob is required. Tested working: - SATA SSD - SATA DVD drive - M.2 SATA - All USB ports - Sdcard - Speakers/headphone jack - Keyboard/touchpad - VGA - mini DisplayPort (Thunderbolt untested) - eDP laptop screen - Camera - Smartcard reader - Internal flashing when IFD is unlocked - Thinkpad basic dock - CMOS options - WLAN - Bluetooth - Ethernet - Using me_cleaner Not working: - libgfxinit - Keyboard backlight - Each boot takes 20s Signed-off-by: Amersel <amersel(a)runbox.me> Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 --- A src/mainboard/lenovo/w541/Kconfig A src/mainboard/lenovo/w541/Kconfig.name A src/mainboard/lenovo/w541/Makefile.inc A src/mainboard/lenovo/w541/acpi/ec.asl A src/mainboard/lenovo/w541/acpi/platform.asl A src/mainboard/lenovo/w541/acpi/superio.asl A src/mainboard/lenovo/w541/acpi_tables.c A src/mainboard/lenovo/w541/board_info.txt A src/mainboard/lenovo/w541/cmos.default A src/mainboard/lenovo/w541/cmos.layout A src/mainboard/lenovo/w541/data.vbt A src/mainboard/lenovo/w541/devicetree.cb A src/mainboard/lenovo/w541/dsdt.asl A src/mainboard/lenovo/w541/gma-mainboard.ads A src/mainboard/lenovo/w541/gpio.c A src/mainboard/lenovo/w541/hda_verb.c A src/mainboard/lenovo/w541/mainboard.c A src/mainboard/lenovo/w541/romstage.c A src/mainboard/lenovo/w541/smihandler.c 19 files changed, 768 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52659/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/52659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Gerrit-Change-Number: 52659 Gerrit-PatchSet: 14 Gerrit-Owner: amersel Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add LTE modem support for drawper
by Tony Huang (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Wisley Chen, Karthik Ramasubramanian. Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55181 ) Change subject: mb/google/dedede/var/drawcia: Add LTE modem support for drawper ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Please help review. Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/55181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Gerrit-Change-Number: 55181 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Jun 2021 03:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Avoid aliasing MMIO writes
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55200 ) Change subject: cpu/x86/lapic: Avoid aliasing MMIO writes ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55200/comment/b920c7a4_3e30069b PS6, Line 8: missing text here -- To view, visit https://review.coreboot.org/c/coreboot/+/55200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75440cb0742eeaa140f49e7e4a4c51a96465441b Gerrit-Change-Number: 55200 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 02:54:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/lapic: Do not inline some utility functions
by Kyösti Mälkki (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55258 ) Change subject: cpu/x86/lapic: Do not inline some utility functions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > So what is the rationale? Is the resulting size smaller? They are not __always_inline and specially enable_lapic() will become more complex for X2APIC state changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/55258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Gerrit-Change-Number: 55258 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 07 Jun 2021 02:52:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: stddef.h: Use compiler macros for built-in integer types
by Jacob Garber (Code Review) 06 Jun '21

06 Jun '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55260 ) Change subject: stddef.h: Use compiler macros for built-in integer types ...................................................................... stddef.h: Use compiler macros for built-in integer types ptrdiff_t, wchar_t, and wint_t are all integer types built-in to the C language (as opposed to being library-only types defined in a header). In the past we had to define these typedefs ourselves because of romcc, but now that it's gone we should use the GCC-provided macros to select the types the compiler expects. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I0874eddf780b6e41ce773ad8b4faa595e4bbd8a7 --- M src/include/stddef.h 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/55260/1 diff --git a/src/include/stddef.h b/src/include/stddef.h index b668b1a..190413c 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -3,10 +3,7 @@ #include <commonlib/helpers.h> -typedef long ptrdiff_t; -#ifndef __SIZE_TYPE__ -#define __SIZE_TYPE__ unsigned long -#endif +typedef __PTRDIFF_TYPE__ ptrdiff_t; typedef __SIZE_TYPE__ size_t; /* There is a GCC macro for a size_t type, but not * for a ssize_t type. Below construct tricks GCC @@ -16,8 +13,8 @@ typedef __SIZE_TYPE__ ssize_t; #undef unsigned -typedef int wchar_t; -typedef unsigned int wint_t; +typedef __WCHAR_TYPE__ wchar_t; +typedef __WINT_TYPE__ wint_t; #define NULL ((void *)0) -- To view, visit https://review.coreboot.org/c/coreboot/+/55260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0874eddf780b6e41ce773ad8b4faa595e4bbd8a7 Gerrit-Change-Number: 55260 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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