coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Update GPIO configuration
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55148 ) Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration ...................................................................... mb/google/guybrush/var/guybrush: Update GPIO configuration Some of the GPIOs are either re-purposed for different use-cases or are unused in upcoming board phase (board version 2). Update the GPIO configuration accordingly. Here are the GPIOs that are updated: GPIO Board Id 1 Board Id 2 ============================================= GPIO31 TP183 EN_SPKR GPIO69 EN_SPKR SD_AUX_REST_L GPIO70 SD_AUX_RESET_L Unused TP27 GPIO74 RAM_ID_CHAN_SEL Unused TP49 BUG=b:189327557, b:188542649, b:188542497 TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is detected fine in Board ID 1. Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55148 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c 2 files changed, 14 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index c89ded2..eb42ab5 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ PAD_GPO(GPIO_29, LOW), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* SPI_CS3_L */ - PAD_NF(GPIO_31, SPI_CS3_L, PULL_NONE), + /* EN_SPKR */ + PAD_GPO(GPIO_31, HIGH), /* EN_PWR_FP */ PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ @@ -79,13 +79,13 @@ PAD_GPI(GPIO_67, PULL_NONE), /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_68, LOW), - /* EN_SPKR */ - PAD_GPO(GPIO_69, HIGH), /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_70, HIGH), + PAD_GPO(GPIO_69, HIGH), + /* Unused TP27 */ + PAD_NC(GPIO_70), /* GPIO_71 - GPIO_73: Not available */ - /* RAM_ID_CHAN_SEL */ - PAD_GPI(GPIO_74, PULL_NONE), + /* Unused TP49 */ + PAD_NC(GPIO_74), /* RAM_ID_2 / DEV_BEEP_LRCLK */ PAD_GPI(GPIO_75, PULL_NONE), /* EN_PP3300_CAM */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 64afa60..05c1542 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -8,8 +8,14 @@ /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_gpio_table[] = { + /* Unused TP183 */ + PAD_NC(GPIO_31), /* EN_SPKR */ - PAD_GPO(GPIO_69, LOW), + PAD_GPO(GPIO_69, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_70, HIGH), + /* RAM_ID_CHAN_SEL */ + PAD_GPI(GPIO_74, PULL_NONE), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/55148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa Gerrit-Change-Number: 55148 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cezanne/psp_verstage: add reset/timer svc
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55137 ) Change subject: cezanne/psp_verstage: add reset/timer svc ...................................................................... cezanne/psp_verstage: add reset/timer svc The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/soc/amd/common/psp_verstage/Makefile.inc M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 4 files changed, 55 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index c0593bf..7ad2149 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -8,8 +8,6 @@ #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> #include <psp_verstage.h> -#include <reset.h> -#include <timer.h> uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { @@ -35,17 +33,3 @@ { return 0; } - -static uint64_t tmp_timer_value = 0; -void timer_monotonic_get(struct mono_time *mt) -{ - mt->microseconds = tmp_timer_value / 1000; - tmp_timer_value++; -} - -void do_board_reset(void) -{ - printk(BIOS_ERR, "Reset not implemented yet.\n"); - while (1) - ; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 70cb369..bd4bec5 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -35,9 +35,8 @@ void svc_delay_in_usec(uint32_t delay) { - uint32_t i; - for (i = 0; i < delay * 1000; i++) - asm volatile ("nop"); + uint32_t unused = 0; + SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); } uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) @@ -97,3 +96,19 @@ SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); return retval; } + +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) +{ + unsigned int retval = 0; + assert(type < PSP_TIMER_TYPE_MAX); + SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval); + return retval; +} + +uint32_t svc_reset_system(enum reset_type reset_type) +{ + unsigned int retval = 0; + assert(reset_type < RESET_TYPE_MAX); + SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval); + return retval; +} diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc index 7272de4..678bc45 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ b/src/soc/amd/common/psp_verstage/Makefile.inc @@ -14,10 +14,10 @@ verstage-y += printk.c verstage-y += psp_verstage.c verstage-y += psp.c -ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) -# cezanne PSP does not support these functions yet (b/187906425) verstage-y += reset.c verstage-y += timer.c +ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) +# cezanne PSP does not support these functions yet (b/187906425) verstage-y += vboot_crypto.c endif diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 25a15e6..75458c3 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -37,6 +37,7 @@ #define SVC_DEBUG_PRINT 0x06 #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_GET_BOOT_MODE 0x1C +#define SVC_DELAY_IN_MICRO_SECONDS 0x2F #define SVC_GET_SPI_INFO 0x60 #define SVC_MAP_SPIROM_DEVICE 0x61 #define SVC_UNMAP_SPIROM_DEVICE 0x62 @@ -44,6 +45,8 @@ #define SVC_UNMAP_FCH_IO_DEVICE 0x64 #define SVC_UPDATE_PSP_BIOS_DIR 0x65 #define SVC_COPY_DATA_FROM_UAPP 0x66 +#define SVC_RESET_SYSTEM 0x67 +#define SVC_READ_TIMER_VAL 0x68 enum psp_boot_mode { PSP_BOOT_MODE_S0 = 0x0, @@ -54,6 +57,13 @@ PSP_BOOT_MODE_S5_WARM = 0x5, }; +enum reset_type +{ + RESET_TYPE_COLD = 0, + RESET_TYPE_WARM = 1, + RESET_TYPE_MAX = 2, +}; + enum fch_io_device { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, @@ -81,6 +91,12 @@ uint32_t SpiBiosSize; }; +enum psp_timer_type { + PSP_TIMER_TYPE_CHRONO = 0, + PSP_TIMER_TYPE_SECURE_RTC = 1, + PSP_TIMER_TYPE_MAX = 2, +}; + /* * Exit to the main Boot Loader. This does not return back to user application. * @@ -206,6 +222,25 @@ uint32_t svc_save_uapp_data(void *address, uint32_t size); /* + * Read timer raw (currently CHRONO and RTC) value + * + * Parameters: + * type - [in] Type of timer UAPP would like to read from + * (currently CHRONO and RTC) + * counter_value - [out] return the raw counter value read from + * RTC or CHRONO_LO/HI counter register + -----------------------------------------------------------------------------*/ +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value); + +/* + * Reset the system + * + * Parameters: + * reset_type - Cold or Warm reset + */ +uint32_t svc_reset_system(enum reset_type reset_type); + +/* * Write postcode to Port-80 * * Parameters: -- To view, visit https://review.coreboot.org/c/coreboot/+/55137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Gerrit-Change-Number: 55137 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: initialize i2c in soc_init
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55136 ) Change subject: psp_verstage: initialize i2c in soc_init ...................................................................... psp_verstage: initialize i2c in soc_init GSC is connected with AP via i2c bus so we need to enable i2c in psp_verstage. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/verstage.c M src/mainboard/google/zork/verstage.c M src/soc/amd/common/psp_verstage/fch.c 3 files changed, 6 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e7543c0..4296729 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -19,7 +19,3 @@ { setup_gpio(); } - -void verstage_mainboard_init(void) -{ -} diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c index dd59e73..3ef0423 100644 --- a/src/mainboard/google/zork/verstage.c +++ b/src/mainboard/google/zork/verstage.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/gpio_banks.h> -#include <amdblocks/i2c.h> #include <baseboard/variants.h> -#include <console/console.h> #include <security/vboot/vboot_common.h> -#include <soc/southbridge.h> static void setup_gpio(void) { @@ -18,20 +15,7 @@ printk(BIOS_DEBUG, "GPIOs setup\n"); } -static void setup_i2c(void) -{ - printk(BIOS_DEBUG, "Setting up i2c\n"); - i2c_soc_early_init(); - printk(BIOS_DEBUG, "i2c setup\n"); -} - void verstage_mainboard_early_init(void) { setup_gpio(); } - -void verstage_mainboard_init(void) -{ - enable_aoac_devices(); - setup_i2c(); -} diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index a032bde..c74e88fd 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/i2c.h> #include <amdblocks/spi.h> #include <arch/exception.h> #include <arch/hlt.h> @@ -155,4 +156,9 @@ { if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) espi_setup(); + + enable_aoac_devices(); + printk(BIOS_DEBUG, "Setting up i2c\n"); + i2c_soc_early_init(); + printk(BIOS_DEBUG, "i2c setup\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Set SaIpuEnable UPD from device state
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55143 ) Change subject: soc/intel/alderlake: Set SaIpuEnable UPD from device state ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55143/comment/779c92ab_02afd7e5 PS1, Line 218: dev = pcidev_path_on_root(SA_DEVFN_IPU); Isn't dev already assigned the way you need it here in line 207? Why do you need to repeat it? -- To view, visit https://review.coreboot.org/c/coreboot/+/55143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Gerrit-Change-Number: 55143 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 05:11:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAY...
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55146 ) Change subject: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD ...................................................................... drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD Tianocore UEFIPAYLOAD now supports SMMSTORE V2, so enable it by default Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55146 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/smmstore/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index ba8268e..13b7312 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -9,6 +9,7 @@ config SMMSTORE_V2 bool "Use version 2 of SMMSTORE API" depends on SMMSTORE + default y if TIANOCORE_UEFIPAYLOAD default n help Version 2 of SMMSTORE allows secure communication with SMM and -- To view, visit https://review.coreboot.org/c/coreboot/+/55146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8 Gerrit-Change-Number: 55146 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55145 ) Change subject: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD ...................................................................... payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD The custom bootsplash option only functions when using the UEFIPAYLOAD payload option, so restrict visibility to when that option is selected. Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55145 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/tianocore/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 9a331a3..cb3ff5d 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -63,8 +63,6 @@ this option, especially if using a debug (vs release) build. Selecting this option will increase the payload size in CBFS by ~220KB. -endif - config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" help @@ -84,6 +82,8 @@ If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. +endif + config TIANOCORE_BOOT_TIMEOUT int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Gerrit-Change-Number: 55145 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... payloads/tianocore: Add Kconfig option to enable cbmem logging Logging to coreboot cbmem, instead of a serial console, was added to MrChromebox's uefipayloadpkg branch. Add a Kconfig option to enable this, and restrict it to the UEFIPAYLOAD payload option, since this feature does not exist in upstream edk2. Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55144 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Benjamin Doron: Looks good to me, but someone else must approve diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e30f570..3d46553 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -148,6 +148,7 @@ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ + CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index c227bf3..9a331a3 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -53,6 +53,18 @@ endchoice +if TIANOCORE_UEFIPAYLOAD + +config TIANOCORE_CBMEM_LOGGING + bool "Enable Tianocore logging to CBMEM" + help + Select this option if you want to enable Tianocore logging to CBMEM. + You may want to increase the default cbmem buffer size when selecting + this option, especially if using a debug (vs release) build. + Selecting this option will increase the payload size in CBFS by ~220KB. + +endif + config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" help diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 7ab4f9e..e23d946 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -30,9 +30,13 @@ BUILD_TYPE=RELEASE endif +ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) +CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/model_206ax/acpi.c: Do not report P_BLK
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55215 ) Change subject: cpu/intel/model_206ax/acpi.c: Do not report P_BLK ...................................................................... cpu/intel/model_206ax/acpi.c: Do not report P_BLK IO MWAIT redirection is disabled, which means reads to the P_LVL2 and P_LVL3 "registers" will never produce any C-state transition requests. Moreover, the register resource descriptors for all reported C-states use the FFixedHW address space, not I/O. Change-Id: I026835dd24d7ac1e1bae2d851e011e1670abaad4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55215 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 526a6d4..f1d03c8 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -306,7 +306,7 @@ void generate_cpu_entries(const struct device *device) { - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; + int coreID, cpuID; int totalcores = dev_count_cpu(); int cores_per_package = get_logical_cores_per_package(); int numcpus = totalcores/cores_per_package; @@ -316,15 +316,9 @@ for (cpuID = 1; cpuID <= numcpus; cpuID++) { for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); + (cpuID-1)*cores_per_package+coreID-1, 0, 0); /* Generate P-state tables */ generate_P_state_entries( -- To view, visit https://review.coreboot.org/c/coreboot/+/55215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I026835dd24d7ac1e1bae2d851e011e1670abaad4 Gerrit-Change-Number: 55215 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/haswell/acpi.c: Do not report P_BLK
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55214 ) Change subject: cpu/intel/haswell/acpi.c: Do not report P_BLK ...................................................................... cpu/intel/haswell/acpi.c: Do not report P_BLK Even if IO MWAIT redirection were enabled, the base address is wrong. Moreover, the register resource descriptors for all reported C-states use the FFixedHW address space, not I/O. Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/haswell/acpi.c 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 8eec704..f20d446 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -333,7 +333,7 @@ void generate_cpu_entries(const struct device *device) { - int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; + int coreID, cpuID; int totalcores = dev_count_cpu(); int cores_per_package = get_logical_cores_per_package(); int numcpus = totalcores/cores_per_package; @@ -343,15 +343,9 @@ for (cpuID = 1; cpuID <= numcpus; cpuID++) { for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); + (cpuID - 1) * cores_per_package+coreID - 1, 0, 0); /* Generate P-state tables */ generate_P_state_entries( -- To view, visit https://review.coreboot.org/c/coreboot/+/55214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d Gerrit-Change-Number: 55214 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
by Werner Zeh (Code Review) 06 Jun '21

06 Jun '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55213 ) Change subject: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR ...................................................................... cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR The MSR only needs to be set when IO MWAIT redirection is to be enabled. Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index beb885e..7a40644 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -172,12 +172,6 @@ msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); - msr.lo &= ~0x7ffff; - msr.lo |= (PMB0_BASE + 4); // LVL_2 base address - msr.lo |= (2 << 16); // CST Range: C7 is max C-state - wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/55213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad Gerrit-Change-Number: 55213 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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