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Change subject: util/sconfig: Fix null pointer dereferences
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52865/comment/06cb003c_a2bad7c0
PS1, Line 9: We need to configure CPU PCIE root port related gpios in early
: boot block stage for CPU root ports to work.
> Hi Furquan, […]
Thanks Maulik. Can you please add that detail to the commit message? It wasn't clear that there is a dependency on FSP-M PCIe configuration.
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Change subject: mb/google/brya: enable DPTF functionality for brya
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/52859/comment/eecff601_7ba43a54
PS1, Line 123: chip drivers/intel/dptf
> As per our understanding, these changes are required as under baseboard changes for brya variants an […]
Hi Sumeet, having gone through 2 programs with this approach (volteer & dedede), I think I'd like to try keeping the DPTF parameters in each overridetree instead of the baseboard.
Several reasons for this:
1) Separate tables depending on FW_CONFIG, see CB:52495, I think this makes it harder to understand lindar's tables
2) Syntax differences between devicetree & override can cause unintended behavior (dedede had to fix several variants with this issue)
3) CB:46874, awkward to disable active policy for fanless devices
WDYT?
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Generate PCI routing table
......................................................................
soc/amd/cezanne: Generate PCI routing table
We use the FSP PCI routing HOB to construct the ACPI _PRT table.
This code was based off of picasso's pcie_gpp.c. The eventual goal is
to make picasso's FSP export the same HOB and then we can move this
code into amd/common.
BUG=b:184766519
TEST=Dump guybrush ACPI table and verify it looks correct.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326
---
A src/soc/amd/cezanne/acpi/pci_int.asl
M src/soc/amd/cezanne/acpi/soc.asl
M src/soc/amd/cezanne/pcie_gpp.c
3 files changed, 306 insertions(+), 3 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names
......................................................................
soc/amd/cezanne: Generate PCI GPP ACPI names
We can generate the names, so there is no need to hard code a table.
This will make the code more generic so it can be reused with picasso in
the future.
BUG=b:184766519
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Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11
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David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 )
Change subject: mb/google/dedede/var/metaknight: Update xhci device tree
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: util/sconfig: Fix null pointer dereferences
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52865/comment/0d237070_67558242
PS1, Line 9: We need to configure CPU PCIE root port related gpios in early
: boot block stage for CPU root ports to work.
> Can you please add the reason why CPU root ports do not work if the pads are configured later on i. […]
Hi Furquan,
FSP is configuring all CPU PCIe root ports in romstage and this GPIO configuration is needed for FSP to configure other PCIe registers. This is the reason if we do it in later stage, we still see CPU PCIe root port init failure.
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52888 )
Change subject: util/sconfig: Fix null pointer dereferences
......................................................................
util/sconfig: Fix null pointer dereferences
Should use `name` instead of `field->name`, because `field is supposed
to be NULL at this point.
TEST=add new field from bits 29-64 to volteer, ensure sconfig prints an
error instead of segfaulting.
Change-Id: I933330494e0b10e8494a92e93d6beb58fbec0bc1
Found-by: Coverity CID 1452916
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M util/sconfig/main.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/52888/1
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 111bb50..e2a0586 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -450,7 +450,7 @@
tmp = bits;
while (tmp) {
if (tmp->start_bit > tmp->end_bit || tmp->end_bit > 63) {
- printf("ERROR: fw_config field %s has invalid range %u-%u\n", field->name,
+ printf("ERROR: fw_config field %s has invalid range %u-%u\n", name,
tmp->start_bit, tmp->end_bit);
exit(1);
}
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