coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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6048 discussions

Change in coreboot[master]: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52763 ) Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52763/comment/191219cd_91182a03 PS1, Line 9: GPIOs can only be updated in gpio_configure_pads_with_override() if they : are present in the base table. If they are not there, the override : does not work. This allows them to be in the base table so that they can : be overridden without changing the existing configuration. > How about instead of requiring that everything be programmed in romstage, we add a check at finalize […] What do you compare against to determine if all GPIOs are programmed as we want it? -- To view, visit https://review.coreboot.org/c/coreboot/+/52763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e5e7b7d30f2c89fa1db375ddba394e6914d97b9 Gerrit-Change-Number: 52763 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 16:49:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52867 ) Change subject: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS ...................................................................... Patch Set 3: (1 comment) File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/c/coreboot/+/52867/comment/7af667b8_2ad932b7 PS3, Line 267: TS_FSP_INITRAM_LOAD TS_FSP_MEMORY_INIT_LOAD -- To view, visit https://review.coreboot.org/c/coreboot/+/52867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Gerrit-Change-Number: 52867 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 16:48:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable support for Chrome OS mode switches
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Anil Kumar K, Shaunak Saha, Maulik V Vaghela, Selma Bensaid, Usha P, Bernardo Perez Priego. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52614 ) Change subject: mb/intel/adlrvp: Enable support for Chrome OS mode switches ...................................................................... Patch Set 2: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/52614/comment/9dcd3a85_64c71888 PS2, Line 83: EC_GOOGLE_CHROMEEC_SWITCHES From jenkins failure: selects EC_GOOGLE_CHROMEEC_SWITCHES which has unmet direct dependencies (EC_GOOGLE_CHROMEEC && VBOOT) Can you move `EC_GOOGLE_CHROMEEC_SWITCHES` under `config VBOOT`? -- To view, visit https://review.coreboot.org/c/coreboot/+/52614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c Gerrit-Change-Number: 52614 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 May 2021 16:47:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Fix null pointer dereferences
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52888 ) Change subject: util/sconfig: Fix null pointer dereferences ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I933330494e0b10e8494a92e93d6beb58fbec0bc1 Gerrit-Change-Number: 52888 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 16:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Bora Guvendik, Maulik V Vaghela, Selma Bensaid. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52865 ) Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52865/comment/06cb003c_a2bad7c0 PS1, Line 9: We need to configure CPU PCIE root port related gpios in early : boot block stage for CPU root ports to work. > Hi Furquan, […] Thanks Maulik. Can you please add that detail to the commit message? It wasn't clear that there is a dependency on FSP-M PCIe configuration. -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Tue, 04 May 2021 16:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/eecff601_7ba43a54 PS1, Line 123: chip drivers/intel/dptf > As per our understanding, these changes are required as under baseboard changes for brya variants an […] Hi Sumeet, having gone through 2 programs with this approach (volteer & dedede), I think I'd like to try keeping the DPTF parameters in each overridetree instead of the baseboard. Several reasons for this: 1) Separate tables depending on FW_CONFIG, see CB:52495, I think this makes it harder to understand lindar's tables 2) Syntax differences between devicetree & override can cause unintended behavior (dedede had to fix several variants with this issue) 3) CB:46874, awkward to disable active policy for fanless devices WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 04 May 2021 16:38:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI GPP ACPI names
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52870 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names ...................................................................... soc/amd/cezanne: Generate PCI GPP ACPI names We can generate the names, so there is no need to hard code a table. This will make the code more generic so it can be reused with picasso in the future. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 --- M src/soc/amd/cezanne/pcie_gpp.c 1 file changed, 9 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52870/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Gerrit-Change-Number: 52870 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Yu-hsuan Hsu, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/51556/comment/ae96f605_c576c88d PS2, Line 16: > Add soc/pci_devs.h, I think. Oops, should have happened in the 3rd commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 16:25:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Yu-hsuan Hsu, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51556 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... soc/amd/cezanne: Generate PCI routing table We use the FSP PCI routing HOB to construct the ACPI _PRT table. This code was based off of picasso's pcie_gpp.c. The eventual goal is to make picasso's FSP export the same HOB and then we can move this code into amd/common. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 --- A src/soc/amd/cezanne/acpi/pci_int.asl M src/soc/amd/cezanne/acpi/soc.asl M src/soc/amd/cezanne/pcie_gpp.c 3 files changed, 306 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/51556/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update xhci device tree
by David Wu (Code Review) 04 May '21

04 May '21

David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede/var/metaknight: Update xhci device tree ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 May 2021 16:20:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021