coreboot-gerrit May 2021

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Change in coreboot[master]: mainboard: Add Synology DS918+
by Name of user not set (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Name of user not set #1003506, Martin Roth, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52594 to look at the new patch set (#6). Change subject: mainboard: Add Synology DS918+ ...................................................................... mainboard: Add Synology DS918+ I'm new to coreboot. This port is based on 4.13, this board boots. Tested with tianocore. Can provide serial logs, original Synology's DSM OS works fine with this port. Can run tests on my board. Now works on Master. Things todo: * polish * I211 ethernet chips don't work in OS * 2nd HSUART Serial doesn't work in OS, only in original DSM. Tried all console=ttyS*,115200 and all 'set tty com*' (as per obsd), probably not cb problem. * Freebsd usb stick causes X86 exception, OpenBSD fails to boot at entry point 0x1001000. Both have apl support. log: https://clbin.com/JrurJ * ... Patch set 2 Reformated gpio part and dsdt. Here are serial logs: https://clbin.com/tHOE7 -- Master branch https://clbin.com/wp4R8 -- 4.13 + seabios, same code except 1 include in dsdt https://clbin.com/iUrgJ -- 4.13 + tianocore, same code... Video test: https://schizoden.xyz/videos/watch/816c5a68-af6f-4dd4-8c7e-43d068410822 Patch set 3/4 More gpio reformating, added data.vbt from vendors bios. * trim spare lines on the end, for jenkins sake Patch set 5/6 Removed data.vbt, causes serial to shut off at post 0x98 Fixed cbfs>mem-mapped area from ifwi + MCACHE -400 err -- .fmd Added cmos.layout cmos.default Edited pci-e devices and turned on vtd in devicetree.cb * forgot to remove dptf, which was added as a test. Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Signed-off-by: mkjOoB <dump(a)schizoden.xyz> --- A src/mainboard/synology/Kconfig A src/mainboard/synology/Kconfig.name A src/mainboard/synology/ds918plus/Kconfig A src/mainboard/synology/ds918plus/Kconfig.name A src/mainboard/synology/ds918plus/Makefile.inc A src/mainboard/synology/ds918plus/board_info.txt A src/mainboard/synology/ds918plus/bootblock.c A src/mainboard/synology/ds918plus/cmos.default A src/mainboard/synology/ds918plus/cmos.layout A src/mainboard/synology/ds918plus/devicetree.cb A src/mainboard/synology/ds918plus/ds918plus.fmd A src/mainboard/synology/ds918plus/dsdt.asl A src/mainboard/synology/ds918plus/early_gpio.c A src/mainboard/synology/ds918plus/gpio.c A src/mainboard/synology/ds918plus/gpio.h A src/mainboard/synology/ds918plus/mainboard.c A src/mainboard/synology/ds918plus/romstage.c 17 files changed, 639 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52594/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 6 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Name of user not set #1003506 Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp1_1: Remove verstage compilation units
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52785 ) Change subject: drivers/intel/fsp1_1: Remove verstage compilation units ...................................................................... drivers/intel/fsp1_1: Remove verstage compilation units Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and therefore verstage is not possible either. Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/fsp1_1/Makefile.inc D src/drivers/intel/fsp1_1/verstage.c 2 files changed, 0 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4b8e0a8..c890f35 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -2,10 +2,6 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -verstage-y += car.c -verstage-y += fsp_util.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c - bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c deleted file mode 100644 index c001b62..0000000 --- a/src/drivers/intel/fsp1_1/verstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <fsp/car.h> -#include <program_loading.h> - -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - run_romstage(); - /* Will actually never return. */ - return NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/52785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09 Gerrit-Change-Number: 52785 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/deltalake: Rearrange slot table for remapping type 9 Slot ID
by Johnny Lin (Code Review) 04 May '21

04 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51389 ) Change subject: mb/ocp/deltalake: Rearrange slot table for remapping type 9 Slot ID ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Can this be merged? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/51389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07bdf7f85f8411e04da8a94da7de1e7b93c9e921 Gerrit-Change-Number: 51389 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 04 May 2021 14:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=n
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52784 ) Change subject: arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=n ...................................................................... arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=n TESTED on qemu/i440fx with VBOOT_SEPARATE_VERSTAGE commented out. Change-Id: I1227feab9ffbbc06e614f297be44fb67f13bda42 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52784 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7dea2ce..a3c61c4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -101,7 +101,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -verstage-y += assembly_entry.S +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += assembly_entry.S verstage-y += boot.c verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S -- To view, visit https://review.coreboot.org/c/coreboot/+/52784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1227feab9ffbbc06e614f297be44fb67f13bda42 Gerrit-Change-Number: 52784 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create pirika variant
by Paul Fagerburg (Code Review) 04 May '21

04 May '21

Attention is currently required from: Paul2 Huang, Kirk Wang, Shou-Chieh Hsu, Karthik Ramasubramanian. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52626 ) Change subject: mb/google/dedede: Create pirika variant ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798 Gerrit-Change-Number: 52626 Gerrit-PatchSet: 2 Gerrit-Owner: Kirk Wang Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kirk Wang Gerrit-Attention: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 14:03:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 04 May '21

04 May '21

Attention is currently required from: Star Labs. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52798 ) Change subject: soc/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 5: (95 comments) File src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/615fa672_1de9c22d PS5, Line 18: _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/b0003793_70d7823f PS5, Line 19: _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/21f70058_7ce1505d PS5, Line 22: _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/5e0c326d_f0507dd1 PS5, Line 23: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/c9371141_1ae89d60 PS5, Line 35: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/eeda9c97_1a62f22d PS5, Line 36: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/1596769b_3127f8d5 PS5, Line 37: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/011ab677_0d52ab42 PS5, Line 38: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/021e6c6d_eb09deb9 PS5, Line 39: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/fb18ab14_e24b1f12 PS5, Line 40: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/89ea203a_4be28f18 PS5, Line 41: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/79884974_7948513b PS5, Line 42: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_BUF(TX_DISABLE) | PAD_IRQ_ROUTE(IOAPIC), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/7528e3ab_e5ff7d4b PS5, Line 43: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/641c02ea_fd3ab0ee PS5, Line 44: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/62f2e422_0661db57 PS5, Line 45: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f00cae9d_249e6aee PS5, Line 46: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/8ba5ebc7_f37e5d7e PS5, Line 47: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/17e04603_7d054c11 PS5, Line 48: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/6f3af9d4_f245637d PS5, Line 49: _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/53bff026_418cd68c PS5, Line 50: _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f686e58a_ad5b4382 PS5, Line 51: _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2a64f1b4_bc4ba645 PS5, Line 52: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/dacfba49_6764a907 PS5, Line 53: _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/e450e0ca_a5938072 PS5, Line 54: _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/11bfbb5e_b00c8cf0 PS5, Line 55: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/0ea61fec_50308687 PS5, Line 58: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/e905818e_9716d895 PS5, Line 59: _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/a0937c55_c69b422b PS5, Line 60: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/460bd3f8_290ca242 PS5, Line 61: _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/1bf1f4be_776db7b4 PS5, Line 62: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/00e64fc0_dc2c5255 PS5, Line 63: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f30ac4ce_4754fcc9 PS5, Line 64: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/4c3ec69b_1b6cbed0 PS5, Line 65: _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/383f5638_0c64d947 PS5, Line 66: _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2fee83ee_f389566c PS5, Line 67: _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/45f4261b_e26dae5e PS5, Line 68: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/b1c6655e_542de86f PS5, Line 71: _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f83e2a33_9de4ef3a PS5, Line 72: _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/615119bb_15807c92 PS5, Line 75: _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/3b3cef66_019283a5 PS5, Line 76: _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2287cffe_433484db PS5, Line 77: _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/d36bd949_c795d8e2 PS5, Line 78: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/1b65fea9_1ad7f15a PS5, Line 79: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/b3becfc9_eddf4210 PS5, Line 80: _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/37470683_b9dbdfe7 PS5, Line 81: _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/ace1815d_039e81ae PS5, Line 82: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/febdc2bb_cbc5ecb3 PS5, Line 83: _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/3cc2a0d3_8f262be1 PS5, Line 84: _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/7037979d_c2ba1fb6 PS5, Line 87: _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(LEVEL) | PAD_BUF(TX_RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f394c5ad_1ccacf36 PS5, Line 88: _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/bade16c3_05a4d80d PS5, Line 89: _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/8bcf1f09_e48030ce PS5, Line 90: _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/1cdf75c6_e03b7813 PS5, Line 91: _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/03b914c7_a82fd441 PS5, Line 92: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/23e82404_0be9a4f1 PS5, Line 93: _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f05703b4_ae808ba8 PS5, Line 94: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/3f727fee_3a07ebf3 PS5, Line 95: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2ccd07cc_acc9faa0 PS5, Line 98: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/6b4c93fd_6b400921 PS5, Line 99: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/12847f66_212b4722 PS5, Line 100: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/d30de6bf_45a1f192 PS5, Line 101: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/44f0dce3_1d55275d PS5, Line 102: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/f7be4971_e1ed33db PS5, Line 103: _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2432840a_ff5aa089 PS5, Line 104: _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/5a125d85_bf12b4ff PS5, Line 105: _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/a54e5c68_1c0efe58 PS5, Line 106: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/06cbf9a6_9936b2fe PS5, Line 107: _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/124b02f2_7286164e PS5, Line 108: _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2cdbfd91_7d5d11e3 PS5, Line 109: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/e7f0d400_6fe58aa2 PS5, Line 110: _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2063059b_073424c5 PS5, Line 111: _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/9c81b8c3_f8e06308 PS5, Line 112: _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/8c6eaaa1_fecba33b PS5, Line 113: _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/1d891d0a_b314d118 PS5, Line 114: _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/6207cc52_bdc3c827 PS5, Line 117: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/31a7bfdb_9a47f02b PS5, Line 118: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/89da980f_4a8d6bfc PS5, Line 119: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/7926bcff_85945407 PS5, Line 120: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/970f12b0_1fae982e PS5, Line 121: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/b68ada96_2876b759 PS5, Line 122: _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/5742d987_3221958e PS5, Line 123: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/cf22f5cd_f413edf2 PS5, Line 124: _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/b1c52469_858baabd PS5, Line 125: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/4c62e52e_069ce039 PS5, Line 126: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/c8207963_fa5669c1 PS5, Line 127: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/20372649_86c07633 PS5, Line 128: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/93b91390_5b559da0 PS5, Line 131: _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/5661fe4b_08f91a00 PS5, Line 132: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/fa965f68_a726fb7d PS5, Line 133: _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/2e16a7f1_77539246 PS5, Line 134: _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/67a7bfb7_197d80d2 PS5, Line 135: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/a91740d1_4ac083b8 PS5, Line 136: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/49da4149_cdbe65f1 PS5, Line 137: _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/0ac23cd1_1d823569 PS5, Line 138: _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118392): https://review.coreboot.org/c/coreboot/+/52798/comment/ad5963fc_0f440d54 PS5, Line 139: _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 5 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 04 May 2021 14:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mainboard: Add Star Labs labtop series
by Star Labs (Code Review) 04 May '21

04 May '21

Attention is currently required from: Star Labs. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52798 to look at the new patch set (#5). Change subject: soc/mainboard: Add Star Labs labtop series ...................................................................... soc/mainboard: Add Star Labs labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 --- M src/ec/starlabs/it8987/Makefile.inc M src/ec/starlabs/it8987/acpi/thermal.asl A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc A src/mainboard/starlabs/labtop/variants/tgl/board.fmd A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb A src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/tgl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/tgl/romstage.c 53 files changed, 2,547 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52798/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 5 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update xhci device tree
by build bot (Jenkins) (Code Review) 04 May '21

04 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede/var/metaknight: Update xhci device tree ...................................................................... Patch Set 1: (36 comments) File src/mainboard/google/dedede/variants/metaknight/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/1a148020_3daa54b4 PS1, Line 20: const struct device *xhci, *hub = NULL, *port = NULL; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/476fd066_4fe8bed0 PS1, Line 20: const struct device *xhci, *hub = NULL, *port = NULL; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/0bee93f5_832f862d PS1, Line 21: const struct drivers_usb_acpi_config *config; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/3be55640_7cbb1cd3 PS1, Line 21: const struct drivers_usb_acpi_config *config; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/9b1be74b_2f657b91 PS1, Line 23: xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/d35c9204_d42b0eb3 PS1, Line 23: xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/ce5a3b49_79938b24 PS1, Line 24: if (!xhci) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/27835926_b99cd138 PS1, Line 24: if (!xhci) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/f9e12fb4_90736ada PS1, Line 25: printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/4d6ecfbe_1c8f3667 PS1, Line 25: printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/b3ef0403_786058f6 PS1, Line 26: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/d28ce786_e7337ad7 PS1, Line 26: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/3f1d1cb9_36110afa PS1, Line 27: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/019b058c_ff4bec95 PS1, Line 27: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/7b6483e0_b8ad4d54 PS1, Line 29: while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/686a55a5_00ac03dd PS1, Line 29: while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/b9847bc9_66c921d3 PS1, Line 30: while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/67598ca9_6f56b333 PS1, Line 30: while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/c11cb842_7dc2007b PS1, Line 31: if ((port->path.usb.port_id != 3)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/6e0c0b5d_17cbc625 PS1, Line 31: if ((port->path.usb.port_id != 3)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/f708ffe7_a83fa185 PS1, Line 32: continue; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/e25d7bea_802fed14 PS1, Line 32: continue; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/dc958c41_45a394af PS1, Line 34: config = config_of(port); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/189957f3_297fb9e8 PS1, Line 34: config = config_of(port); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/8feeff47_403c0f36 PS1, Line 35: if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/d82611de_ae93584c PS1, Line 35: if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/bc963f1e_7b8c5db2 PS1, Line 36: /* Set 1A HDMI configuration */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/3bf4bd58_1ef41c18 PS1, Line 37: } else if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/6e9e4529_045a4553 PS1, Line 37: } else if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/9664b489_e1dcf43b PS1, Line 38: /* Set LTE HDMI configuration */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/787bcdfa_b07767af PS1, Line 39: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/1b0a5ed6_ae47fc04 PS1, Line 39: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/7fe4b271_9ba91c9a PS1, Line 40: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/0b2ddaad_3e0ec0a7 PS1, Line 40: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/c05cb113_3f944942 PS1, Line 41: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118390): https://review.coreboot.org/c/coreboot/+/52887/comment/1be89be1_d12d13d5 PS1, Line 41: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 May 2021 13:17:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update xhci device tree
by David Wu (Code Review) 04 May '21

04 May '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede/var/metaknight: Update xhci device tree ...................................................................... mb/google/dedede/var/metaknight: Update xhci device tree Update xhci device tree to fix can not observe LTE ACPI objects in the SSDT. BUG=b:186380807 TEST=build and boot to OS. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/metaknight/variant.c 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/52887/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 26afb69..6d544b5 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -40,10 +40,17 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + variant_devtree_update(); + if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)) mainboard_update_soc_chip_config(); } +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + static void mainboard_dev_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index e7bfd86..a3dcd91 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -39,4 +39,7 @@ /* Allow each variants to customize SMI sleep flow. */ void variant_smi_sleep(u8 slp_typ); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/metaknight/variant.c b/src/mainboard/google/dedede/variants/metaknight/variant.c index 2540fc7..cf97496 100644 --- a/src/mainboard/google/dedede/variants/metaknight/variant.c +++ b/src/mainboard/google/dedede/variants/metaknight/variant.c @@ -3,7 +3,10 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <delay.h> +#include <fw_config.h> #include <gpio.h> +#include <soc/pci_devs.h> +#include <console/console.h> static void power_off_lte_module(void) { @@ -12,6 +15,32 @@ gpio_output(GPP_A10, 0); } +static void update_xhci_devtree(void) +{ + const struct device *xhci, *hub = NULL, *port = NULL; + const struct drivers_usb_acpi_config *config; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + if ((port->path.usb.port_id != 3)) + continue; + + config = config_of(port); + if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI))) { + /* Set 1A HDMI configuration */ + } else if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) { + /* Set LTE HDMI configuration */ + } + } + } +} + void variant_smi_sleep(u8 slp_typ) { /* @@ -21,3 +50,8 @@ if (slp_typ == ACPI_S5) power_off_lte_module(); } + +void variant_devtree_update(void) +{ + update_xhci_devtree(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Create volet variant
by Sheng-Liang Pan (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52871 ) Change subject: mb/google/volteer: Create volet variant ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Gerrit-Change-Number: 52871 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 12:48:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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