coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
by Martin Roth (Code Review) 04 May '21

04 May '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52866 ) Change subject: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1 Gerrit-Change-Number: 52866 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
by Martin Roth (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Andrey Petrov, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52866 ) Change subject: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/api.h: https://review.coreboot.org/c/coreboot/+/52866/comment/73a40308_cf39e743 PS1, Line 75: save and restore registers > This seems like a problem with the FSP implementation itself. […] Sure, but this is being done on the mainboard level, not the platform level. Imagine that you're a developer who doesn't work at Google and can't just get the FSP vendor to fix the issue. What's the recourse? -- To view, visit https://review.coreboot.org/c/coreboot/+/52866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1 Gerrit-Change-Number: 52866 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 15:10:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS
by Martin Roth (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52867 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS ...................................................................... drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS The loads of the FSPM and FSPS binaries are not insignificant amounts of time, and without these timestamps, it's not clear what's going on in those time blocks. For FSPM, the timestamps can run together to make it look like that time is still part of the romstage init time. Example: 6:end of verified boot 387,390 (5,402) 13:starting to load romstage 401,931 (14,541) 14:finished loading romstage 420,560 (18,629) 970:loading FSP-M 450,698 (30,138) 15:starting LZMA decompress (ignore for x86) 464,173 (13,475) 16:finished LZMA decompress (ignore for x86) 517,860 (53,687) ... 9:finished loading ramstage 737,191 (18,377) 10:start of ramstage 757,584 (20,393) 30:device enumeration 790,382 (32,798) 971:loading FSP-S 840,186 (49,804) 15:starting LZMA decompress (ignore for x86) 853,834 (13,648) 16:finished LZMA decompress (ignore for x86) 888,830 (34,996) BUG=None TEST=Build & Boot guybrush, look at timestamps. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/52867/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Gerrit-Change-Number: 52867 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: remove duplicate PL2 override
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52858 ) Change subject: soc/intel/alderlake: remove duplicate PL2 override ...................................................................... soc/intel/alderlake: remove duplicate PL2 override PL2 override value is already declared under common code in power_limit.h file. Removing this duplicate PL2 override from soc specific header file. BRANCH=None BUG=None TEST=Built and tested on brya Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 201150e..fb9dd73 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -162,8 +162,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/52858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Gerrit-Change-Number: 52858 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: remove duplicate PL2 override
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Paul Menzel, Sumeet R Pawnikar, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52858 ) Change subject: soc/intel/alderlake: remove duplicate PL2 override ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Gerrit-Change-Number: 52858 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 15:03:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52846 ) Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Gerrit-Change-Number: 52846 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52845 ) Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Gerrit-Change-Number: 52845 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52844 ) Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Gerrit-Change-Number: 52844 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52842 ) Change subject: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Gerrit-Change-Number: 52842 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: Kconfig: replace `def_bool n` by `bool`
by Michael Niewöhner (Code Review) 04 May '21

04 May '21

Attention is currently required from: Nico Huber, Martin Roth, Werner Zeh. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52809 ) Change subject: treewide: Kconfig: replace `def_bool n` by `bool` ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > > It's actually the other way round. Options in `src/mainboards/Kconfig` and below are included before others (soc, drivers, etc.). So, the "first declaration" is the one in the mainboards. Only when a mainboard does not specify a option that has `def_bool` (or `bool; default n`) the soc/driver/... option is used. > > I missed that you excluded cases there where the mainboard Kconfig > only specifies a default and no type. Actually, I'm not sure right > now about the subtle differences this makes. Having (no) type at the mainboard level didn't seem to make a difference, since we're not overriding types (not sure if that'd be possible). -- To view, visit https://review.coreboot.org/c/coreboot/+/52809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e89c66d18b7b3a5ac425eacea10df8c013814f Gerrit-Change-Number: 52809 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 May 2021 14:52:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2021