coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/alderlake: remove duplicate PL2 override
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52858 ) Change subject: soc/intel/alderlake: remove duplicate PL2 override ...................................................................... soc/intel/alderlake: remove duplicate PL2 override PL2 override value is already declared under common code in power_limit.h file. Removing this duplicate PL2 override from soc specific header file. BRANCH=None BUG=None TEST=Built and tested on brya Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 201150e..fb9dd73 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -162,8 +162,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/52858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Gerrit-Change-Number: 52858 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: remove duplicate PL2 override
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Paul Menzel, Sumeet R Pawnikar, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52858 ) Change subject: soc/intel/alderlake: remove duplicate PL2 override ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Gerrit-Change-Number: 52858 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 15:03:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52846 ) Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Gerrit-Change-Number: 52846 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52845 ) Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Gerrit-Change-Number: 52845 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52844 ) Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Gerrit-Change-Number: 52844 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:54:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52842 ) Change subject: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Gerrit-Change-Number: 52842 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: Kconfig: replace `def_bool n` by `bool`
by Michael Niewöhner (Code Review) 04 May '21

04 May '21

Attention is currently required from: Nico Huber, Martin Roth, Werner Zeh. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52809 ) Change subject: treewide: Kconfig: replace `def_bool n` by `bool` ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > > It's actually the other way round. Options in `src/mainboards/Kconfig` and below are included before others (soc, drivers, etc.). So, the "first declaration" is the one in the mainboards. Only when a mainboard does not specify a option that has `def_bool` (or `bool; default n`) the soc/driver/... option is used. > > I missed that you excluded cases there where the mainboard Kconfig > only specifies a default and no type. Actually, I'm not sure right > now about the subtle differences this makes. Having (no) type at the mainboard level didn't seem to make a difference, since we're not overriding types (not sure if that'd be possible). -- To view, visit https://review.coreboot.org/c/coreboot/+/52809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e89c66d18b7b3a5ac425eacea10df8c013814f Gerrit-Change-Number: 52809 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 May 2021 14:52:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52859/comment/1b5ad243_aa08dadc PS1, Line 7: enable DPTF functionality for brya > Duplicate of CB:52691? This CL has generic/common changes for baseboard. File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/afba573e_2ea019cb PS1, Line 123: chip drivers/intel/dptf > Shouldn't these changes go into overridetree? As per our understanding, these changes are required as under baseboard changes for brya variants and these are generic/common changes which will be default under /brya/variants/"baseboard"/ in devicetree file. On top of these ODM/OEM can change/over write above (baseboard/devicetree.cb) changes for their design specific changes under /brya/variants/"Design1" in overridetree.cb file. Also, another different ODM/OEM can add their design specific changes under /brya/variants/"Design2" in overridetree.cb file. -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 14:49:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Synology DS918+
by build bot (Jenkins) (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Name of user not set #1003506, Martin Roth, Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52594 ) Change subject: mainboard: Add Synology DS918+ ...................................................................... Patch Set 6: (62 comments) File src/mainboard/synology/ds918plus/early_gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/8365a377_0c47faff PS6, Line 40: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/1e8b55ac_5cdc0723 PS6, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/bb26dbac_4b29a9b8 PS6, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/620679d0_fce96b13 PS6, Line 60: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/9b0432ec_d69e5b47 PS6, Line 61: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters File src/mainboard/synology/ds918plus/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/cfe73b4d_1169db8a PS6, Line 47: PAD_CFG_GPI_APIC_IOS(GPIO_33, DN_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/5f1702f5_c72c9edb PS6, Line 52: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/6ff70d56_15394456 PS6, Line 53: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/2dc5f77b_07424e3d PS6, Line 54: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/c9bb3c18_4b5f618b PS6, Line 55: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/a4c63472_9123d42a PS6, Line 56: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/e3ac0ca0_28abb5ab PS6, Line 57: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/65d2ac0b_ba1e6c59 PS6, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART1_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/4be54555_7099bb6d PS6, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/1f5c09a5_fb26ea52 PS6, Line 85: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/e94ff6b6_93ac97c4 PS6, Line 86: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_RSP, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/0f872539_a7fdc9dd PS6, Line 102: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/88fafd22_c6393553 PS6, Line 103: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/943bad0b_981c860b PS6, Line 104: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/7f6e3283_e19ae393 PS6, Line 114: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS0, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/dc1c26db_aa35d610 PS6, Line 115: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS1, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/04caf3df_a7287f61 PS6, Line 117: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_RXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/641957ec_7f44a7ba PS6, Line 118: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_TXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/725c8a01_4ecacc39 PS6, Line 119: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_CLK, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/b9f89da1_278f9661 PS6, Line 121: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_RESET_B, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/183a3fc2_7645f3c5 PS6, Line 126: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_STDBY, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/f04f2be3_73ffbbb8 PS6, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_81, DN_20K, DEEP, NF2, TxDRxE, ENPD), /* AVS_I2C4_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/402c7c15_c7f3331b PS6, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_DMIC_DATA_2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/892e4359_5d8713a8 PS6, Line 147: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_91, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_I2S3_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/83e78156_6728e6f8 PS6, Line 157: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_CLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/b63d6874_4b479e9d PS6, Line 158: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/7e7524db_e145205a PS6, Line 159: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/c289359a_eb7fc84c PS6, Line 160: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/5febd422_48368e5a PS6, Line 161: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/e677cfd0_80921564 PS6, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/bc2eec39_db9f648b PS6, Line 178: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/c72750b0_f409c9c3 PS6, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/e1541d1b_0edaa52c PS6, Line 180: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/2d238ade_ccc4185f PS6, Line 181: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/4005d184_9fed7869 PS6, Line 182: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/8e5e33da_845cbb43 PS6, Line 183: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/fea2654e_71f1ac2a PS6, Line 184: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/544e57e8_ec0d5d91 PS6, Line 185: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/96e2ff43_6795b650 PS6, Line 186: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/8633ad50_5726cd46 PS6, Line 187: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_134, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/d4d6ea9f_b9ba330c PS6, Line 188: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_135, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/ee46a0ed_ad011c24 PS6, Line 189: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_136, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/1c4e959e_5fe90e6d PS6, Line 190: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_137, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/9052ff2c_1d81329f PS6, Line 191: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/54e95774_98f00bd3 PS6, Line 192: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/a3b11792_a471d237 PS6, Line 203: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ0_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/d779208e_33a79af9 PS6, Line 204: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/eb7386c2_7db4d381 PS6, Line 205: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ2_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/c4f864f0_619d7872 PS6, Line 206: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_212, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ3_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/178d7c91_1db4c632 PS6, Line 216: PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/aff151db_82d9886c PS6, Line 221: PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 1, DEEP, UP_20K, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/7a2d1a1e_25fd8f8c PS6, Line 264: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/cbcf18bc_274d49b7 PS6, Line 265: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/378464d9_31da75a5 PS6, Line 266: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/7d64b98e_d6093eee PS6, Line 267: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/3fac4cd3_fc5ba3d4 PS6, Line 268: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118393): https://review.coreboot.org/c/coreboot/+/52594/comment/aef654e2_6a5335c5 PS6, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAMEB */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 6 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Name of user not set #1003506 Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 04 May 2021 14:28:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Synology DS918+
by Name of user not set (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Name of user not set #1003506, Martin Roth, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52594 to look at the new patch set (#6). Change subject: mainboard: Add Synology DS918+ ...................................................................... mainboard: Add Synology DS918+ I'm new to coreboot. This port is based on 4.13, this board boots. Tested with tianocore. Can provide serial logs, original Synology's DSM OS works fine with this port. Can run tests on my board. Now works on Master. Things todo: * polish * I211 ethernet chips don't work in OS * 2nd HSUART Serial doesn't work in OS, only in original DSM. Tried all console=ttyS*,115200 and all 'set tty com*' (as per obsd), probably not cb problem. * Freebsd usb stick causes X86 exception, OpenBSD fails to boot at entry point 0x1001000. Both have apl support. log: https://clbin.com/JrurJ * ... Patch set 2 Reformated gpio part and dsdt. Here are serial logs: https://clbin.com/tHOE7 -- Master branch https://clbin.com/wp4R8 -- 4.13 + seabios, same code except 1 include in dsdt https://clbin.com/iUrgJ -- 4.13 + tianocore, same code... Video test: https://schizoden.xyz/videos/watch/816c5a68-af6f-4dd4-8c7e-43d068410822 Patch set 3/4 More gpio reformating, added data.vbt from vendors bios. * trim spare lines on the end, for jenkins sake Patch set 5/6 Removed data.vbt, causes serial to shut off at post 0x98 Fixed cbfs>mem-mapped area from ifwi + MCACHE -400 err -- .fmd Added cmos.layout cmos.default Edited pci-e devices and turned on vtd in devicetree.cb * forgot to remove dptf, which was added as a test. Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Signed-off-by: mkjOoB <dump(a)schizoden.xyz> --- A src/mainboard/synology/Kconfig A src/mainboard/synology/Kconfig.name A src/mainboard/synology/ds918plus/Kconfig A src/mainboard/synology/ds918plus/Kconfig.name A src/mainboard/synology/ds918plus/Makefile.inc A src/mainboard/synology/ds918plus/board_info.txt A src/mainboard/synology/ds918plus/bootblock.c A src/mainboard/synology/ds918plus/cmos.default A src/mainboard/synology/ds918plus/cmos.layout A src/mainboard/synology/ds918plus/devicetree.cb A src/mainboard/synology/ds918plus/ds918plus.fmd A src/mainboard/synology/ds918plus/dsdt.asl A src/mainboard/synology/ds918plus/early_gpio.c A src/mainboard/synology/ds918plus/gpio.c A src/mainboard/synology/ds918plus/gpio.h A src/mainboard/synology/ds918plus/mainboard.c A src/mainboard/synology/ds918plus/romstage.c 17 files changed, 639 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52594/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 6 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Name of user not set #1003506 Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021