Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52858 )
Change subject: soc/intel/alderlake: remove duplicate PL2 override ......................................................................
soc/intel/alderlake: remove duplicate PL2 override
PL2 override value is already declared under common code in power_limit.h file. Removing this duplicate PL2 override from soc specific header file.
BRANCH=None BUG=None TEST=Built and tested on brya
Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/chip.h 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 201150e..fb9dd73 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -162,8 +162,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;