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Hello build bot (Jenkins), Selma Bensaid, Maulik V Vaghela,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
---
M src/mainboard/intel/adlrvp/early_gpio_m.c
1 file changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52865/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52894 )
Change subject: include/console: Fix comments for FSP Notify End of Firmware postcodes
......................................................................
include/console: Fix comments for FSP Notify End of Firmware postcodes
Postcode 0x88 is getting called prior to FSP notify and postcode 0x89
after calling FSP notify. Both these FSP notify calls are attached
with End of Firmware event.
Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/console/post_codes.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52894/1
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 677cd36..69047f8 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -204,14 +204,14 @@
#define POST_ENTRY_RAMSTAGE 0x80
/**
- * \brief Before calling FSP Notify before End of Firmware
+ * \brief Before calling FSP Notify at End of Firmware
*
* Going to call into FSP binary for Notify phase
*/
#define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88
/**
- * \brief Before calling FSP Notify after End of Firmware
+ * \brief After calling FSP Notify at End of Firmware
*
* Going to call into FSP binary for Notify phase
*/
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Gerrit-Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23
Gerrit-Change-Number: 52894
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52893 )
Change subject: include/console: Align ramstage Boot State Machine postcodes
......................................................................
include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.
Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/console/post_codes.h
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52893/1
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index ee74dcb..677cd36 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -182,14 +182,6 @@
#define POST_PRE_HARDWAREMAIN 0x79
/**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE 0x80
-
-/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()
@@ -204,6 +196,14 @@
#define POST_BS_PAYLOAD_BOOT 0x7b
/**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_RAMSTAGE 0x80
+
+/**
* \brief Before calling FSP Notify before End of Firmware
*
* Going to call into FSP binary for Notify phase
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Change subject: mb/intel/adlrvp: Enable support for Chrome OS mode switches
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52614/comment/6957dee1_6e5a671f
PS3, Line 9: Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
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Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
......................................................................
Patch Set 23: Code-Review+2
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Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
......................................................................
Patch Set 23:
(2 comments)
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/51649/comment/7f599821_df2ec6fc
PS22, Line 331: tcss_configure_aux_bias_pads
> Sure, then `tcss_configure` has to take the parameters too, b/c the field exists in the SoC `chip. […]
Yeah. I was thinking we can also move this into `soc_intel_common_config` (https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…). And then tcss common block driver can call `chip_get_common_soc_structure()` to get access to the required info. But, I think it is fine either ways i.e. passing in information into `tcss_configure` or adding it to the common structure.
https://review.coreboot.org/c/coreboot/+/51649/comment/2ac92e08_a397e225
PS22, Line 333: MAX_TYPE_C_PORTS
> Do you know something I don't? 😜 […]
Haha, you know much more than me ;).
I said Kconfig because if we determine that some platform supports different number of type-C ports, then we don't have to move this to a .h file in SoC. I find that always very error-prone. There is no clear way to document what all is expected from SoC and what a particular definition really means. Also, if different lines of SoC (e.g. Intel-U v/s Intel-Y for the same SoC) supports different number of type-C ports, then it becomes messy in .h file. We can also create a table for `tcss_info` and use that to capture all TCSS related info if Kconfig doesn't seem right.
Anyways, it is not a problem right now, but I suspect we would have to deal with it at some point.
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Change subject: util/intelp2m: Set GO111MODULE environment parameter explicitly
......................................................................
Patch Set 1: Code-Review+2
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 14:
(2 comments)
File src/soc/intel/xeon_sp/include/soc/hest.h:
https://review.coreboot.org/c/coreboot/+/52090/comment/45756dc2_7a163dc9
PS13, Line 18:
: typedef struct acpi_gen_regaddr1 {
: u8 space_id; /* Address space ID */
: u8 bit_width; /* Register size in bits */
: u8 bit_offset; /* Register bit offset */
: u8 access_size; /* Access size since ACPI 2.0c */
: u64 addr; /* Register address */
: } __packed acpi_addr64_t;
> This is in `acpi. […]
Done...fixed.
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/3656cc16_0d856e3b
PS13, Line 292: /* Reserve memory for Enhanced error logging */
: if (CONFIG(SOC_RAS_ELOG)) {
: base_kb = cbmem_top_addr >> 10;
: size_kb = CONFIG_ERROR_LOG_BUFFER_SIZE >> 10;
: LOG_MEM_RESOURCE("elog_sts_blk", dev, index, base_kb, size_kb);
: reserved_ram_resource(dev, index++, base_kb, size_kb);
: elog_addr = cbmem_top_addr;
: printk(BIOS_DEBUG, "%s elog_addr = %llx size = %x\n",
: __func__, elog_addr, CONFIG_ERROR_LOG_BUFFER_SIZE);
: }
:
> Looks like the reserved region is placed right above CBMEM top. […]
So previously I started out using cbmem_add() for reserving this memory and for the EINJ patch. The problem was; cbmem_add labels the memory as type 16 in e820 table. Type 16 is Unknown to the OS (cat /proc/iomem). So using the cbmem_add mechanism, the APEI driver fails to load becuase the memory is unknown. If I reserve the memory as a dram resource like above, its marked as "reserved" in E820 table then APEI driver loads properly since it recognizes this memory to be valid (which is reserved).
Regarding the overlap, I'm not sure how to notify cbmem of this memory reservation. I'm not aware of a specific method that allows adding of "reserved" memory. If you know of one, let me know and I can try it out.
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Hello build bot (Jenkins), Patrick Georgi, Jonathan Zhang, Rocky Phagura, Angel Pons, Patrick Rudolph, Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Martin Roth, Johnny Lin, Tim Wawrzynczak, David Hendricks, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support.
This involves a few different parts: (1) The ACPI HEST table which is filled
with the appropriate fields (2) Reserved memory which is used by runtime
SW to provide error information. OS will not accept a HEST table with
this memory set to 0.
The ASL code to enable APEI bit will be submitted in a separate patch.
Tested on DeltaLake mainboard with following options enabled
SOC_INTEL_XEON_RAS
After boot to Linux, the following will show in dmesg:
HEST: Table parsing has been initialized
Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd
Signed-off-by: Rocky Phagura <rphagura(a)fb.com>
---
M src/soc/intel/common/block/include/intelblocks/nvs.h
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/include/soc/hest.h
M src/soc/intel/xeon_sp/nb_acpi.c
A src/soc/intel/xeon_sp/ras/Kconfig
A src/soc/intel/xeon_sp/ras/Makefile.inc
A src/soc/intel/xeon_sp/ras/hest.c
M src/soc/intel/xeon_sp/uncore.c
9 files changed, 169 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52090/14
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