coreboot-gerrit May 2021

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Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Subrata Banik (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... Patch Set 1: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52893/comment/99f57b87_4d860067 PS1, Line 182: 0x79 > Just noticed that we have duplicate 0x79 post codes. Yes, i was adding 0x7c for POST_PRE_HARDWAREMAIN, submitting the CL, hopes that fine, because we have 0x7b-0x7f empty. -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix comments for FSP Notify End of Firmware postcodes
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52894 ) Change subject: include/console: Fix comments for FSP Notify End of Firmware postcodes ...................................................................... Patch Set 1: (3 comments) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52894/comment/da6175c5_07146876 PS1, Line 209: phase Probably say "(end of firmware)" after phase? Same for after call? https://review.coreboot.org/c/coreboot/+/52894/comment/42935a25_6518ea45 PS1, Line 256: before This seems to have the same problem. https://review.coreboot.org/c/coreboot/+/52894/comment/b8a837cb_11b4fe54 PS1, Line 260: POST_FSP_NOTIFY_BEFORE_FINALIZE Just noticed that we are incorrectly using this even after finalize notification is done: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… Same for enumeration phase. -- To view, visit https://review.coreboot.org/c/coreboot/+/52894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Gerrit-Change-Number: 52894 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:26:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Bora Guvendik (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Selma Bensaid. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52865 ) Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52865/comment/5ea06f3c_9dd1c7f4 PS1, Line 9: We need to configure CPU PCIE root port related gpios in early : boot block stage for CPU root ports to work. > Thanks Maulik. […] Thanks Maulik. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:22:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52893/comment/0a7c152d_a97a874b PS1, Line 182: 0x79 Just noticed that we have duplicate 0x79 post codes. -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Bora Guvendik (Code Review) 04 May '21

04 May '21

Attention is currently required from: Bora Guvendik, Maulik V Vaghela, Selma Bensaid. Hello build bot (Jenkins), Selma Bensaid, Maulik V Vaghela, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52865 to look at the new patch set (#2). Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work due to the dependency on FSP-M PCIe configuration. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 --- M src/mainboard/intel/adlrvp/early_gpio_m.c 1 file changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52865/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/console: Fix comments for FSP Notify End of Firmware postcodes
by Subrata Banik (Code Review) 04 May '21

04 May '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52894 ) Change subject: include/console: Fix comments for FSP Notify End of Firmware postcodes ...................................................................... include/console: Fix comments for FSP Notify End of Firmware postcodes Postcode 0x88 is getting called prior to FSP notify and postcode 0x89 after calling FSP notify. Both these FSP notify calls are attached with End of Firmware event. Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/console/post_codes.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52894/1 diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 677cd36..69047f8 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -204,14 +204,14 @@ #define POST_ENTRY_RAMSTAGE 0x80 /** - * \brief Before calling FSP Notify before End of Firmware + * \brief Before calling FSP Notify at End of Firmware * * Going to call into FSP binary for Notify phase */ #define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 /** - * \brief Before calling FSP Notify after End of Firmware + * \brief After calling FSP Notify at End of Firmware * * Going to call into FSP binary for Notify phase */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Gerrit-Change-Number: 52894 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Subrata Banik (Code Review) 04 May '21

04 May '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... include/console: Align ramstage Boot State Machine postcodes This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/console/post_codes.h 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52893/1 diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ee74dcb..677cd36 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -182,14 +182,6 @@ #define POST_PRE_HARDWAREMAIN 0x79 /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -204,6 +196,14 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable support for Chrome OS mode switches
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Anil Kumar K, Shaunak Saha, Maulik V Vaghela, Selma Bensaid, Usha P, Bernardo Perez Priego. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52614 ) Change subject: mb/intel/adlrvp: Enable support for Chrome OS mode switches ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52614/comment/6957dee1_6e5a671f PS3, Line 9: Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> This is added in the last part of the commit message along with the "Change-Id" field. -- To view, visit https://review.coreboot.org/c/coreboot/+/52614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c Gerrit-Change-Number: 52614 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 May 2021 17:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

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Change in coreboot[master]: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Shaunak Saha, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51649 ) Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads ...................................................................... Patch Set 23: (2 comments) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/51649/comment/7f599821_df2ec6fc PS22, Line 331: tcss_configure_aux_bias_pads > Sure, then `tcss_configure` has to take the parameters too, b/c the field exists in the SoC `chip. […] Yeah. I was thinking we can also move this into `soc_intel_common_config` (https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…). And then tcss common block driver can call `chip_get_common_soc_structure()` to get access to the required info. But, I think it is fine either ways i.e. passing in information into `tcss_configure` or adding it to the common structure. https://review.coreboot.org/c/coreboot/+/51649/comment/2ac92e08_a397e225 PS22, Line 333: MAX_TYPE_C_PORTS > Do you know something I don't? 😜 […] Haha, you know much more than me ;). I said Kconfig because if we determine that some platform supports different number of type-C ports, then we don't have to move this to a .h file in SoC. I find that always very error-prone. There is no clear way to document what all is expected from SoC and what a particular definition really means. Also, if different lines of SoC (e.g. Intel-U v/s Intel-Y for the same SoC) supports different number of type-C ports, then it becomes messy in .h file. We can also create a table for `tcss_info` and use that to capture all TCSS related info if Kconfig doesn't seem right. Anyways, it is not a problem right now, but I suspect we would have to deal with it at some point. -- To view, visit https://review.coreboot.org/c/coreboot/+/51649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Gerrit-Change-Number: 51649 Gerrit-PatchSet: 23 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 17:41:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021