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Change subject: mb/google/volteer: Create volet variant
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
......................................................................
Patch Set 22:
(3 comments)
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/51649/comment/16533a28_7b66e34a
PS22, Line 325: cpu_pid
> Isn't this the same as cpu_portid above?
haha oh yeah 😊
https://review.coreboot.org/c/coreboot/+/51649/comment/9cc91249_3e7db066
PS22, Line 331: tcss_configure_aux_bias_pads
> Now that this function is implemented in the common tcss driver, should it be called from `tcss_conf […]
Sure, then `tcss_configure` has to take the parameters too, b/c the field exists in the SoC `chip.h` and common code can't include that file.
https://review.coreboot.org/c/coreboot/+/51649/comment/2f5b0c7b_47c0acad
PS22, Line 333: MAX_TYPE_C_PORTS
> Not for this change, but I think we should change this to a Kconfig. […]
Do you know something I don't? 😜
I don't know if a Kconfig makes sense, it's not something that the user can change (it's a property of the SoC itself)?
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Hello build bot (Jenkins), Shaunak Saha, Patrick Georgi, Martin Roth, Furquan Shaikh, Angel Pons, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
......................................................................
soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.
BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
---
M src/mainboard/google/volteer/variants/eldrid/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
M src/mainboard/google/volteer/variants/malefor/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/google/volteer/variants/volteer/overridetree.cb
M src/mainboard/google/volteer/variants/volteer2/overridetree.cb
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
A src/soc/intel/tigerlake/include/soc/tcss.h
13 files changed, 86 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/51649/23
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52589 )
Change subject: soc/intel/tigerlake: Add known GPIO virtual wire information
......................................................................
Patch Set 7: Code-Review+2
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Change subject: soc/intel/common: Add virtual wire mapping entries to GPIO communities
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/intel/common: Add virtual wire mapping entries to GPIO communities
......................................................................
Patch Set 5:
(4 comments)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/52588/comment/15cffdbe_4b1be8ee
PS4, Line 784: comm->vw_entries[i].first_pad
> Shouldn't this be `pad - comm->vw_entries[i]. […]
Done
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/52588/comment/377c1cc6_ab7b93c5
PS4, Line 133:
> nit: use tab like other members?
The other struct entries don't have one between `struct` and the rest of the type, but they do after the full type name, I can add it there.
https://review.coreboot.org/c/coreboot/+/52588/comment/ffe46595_b6489276
PS4, Line 133: vw_entries
> Should we add a comment here that the entries are supposed to be in the order in which the groups ma […]
Done
https://review.coreboot.org/c/coreboot/+/52588/comment/8fdda651_ff0b0cbf
PS4, Line 252: it will return 1, and vw_index and vw_bit will be set to -1
> Needs update.
Done
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Change subject: soc/intel/tigerlake: Add known GPIO virtual wire information
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/tigerlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/52589/comment/1acc7b81_7788f793
PS6, Line 106: 0x10
> Might be good to add a macro for this.
Done
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/common: Add virtual wire mapping entries to GPIO communities
......................................................................
soc/intel/common: Add virtual wire mapping entries to GPIO communities
Some SoCs may define virtual wire entries for certain GPIOs. This patch
allows SoC code to provide the mappings from GPIO pads to virtual wire
indexes and bits when they are provided. Also a function
`gpio_get_vw_info` is added to return this information.
Change-Id: I87adf0ca06cb5b7969bb2c258d6daebd44bb9748
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
2 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/52588/5
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52589
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Add known GPIO virtual wire information
......................................................................
soc/intel/tigerlake: Add known GPIO virtual wire information
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at
least some of their groups; add the known information into the community
definitions.
Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/tigerlake/gpio.c
1 file changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/52589/7
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