coreboot-gerrit May 2021

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Arthur Heymans (Code Review) 04 May '21

04 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" This reverts commit 8122b3f6123158024ed2844af17289a9abb98036. This broke DMAR. DRHD defines the scope of the device entries below. Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52898/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 3b2fba9..19c3921 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -198,6 +198,19 @@ if (!reg_base) return current; + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + // Add PCH IOAPIC if (socket == 0 && stack == CSTACK) { union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); @@ -263,19 +276,6 @@ } } - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - acpi_dmar_drhd_fixup(tmp, current); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/52898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Gerrit-Change-Number: 52898 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52896 ) Change subject: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/fsp/fsp-acpi.c: https://review.coreboot.org/c/coreboot/+/52896/comment/884e47ec_8f97b896 PS1, Line 18: add_agesa_fsp_acpi_table Should we add alib into the name and drop the name parameter? This no longer searches for specific tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/52896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Gerrit-Change-Number: 52896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 18:41:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 1: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/5aaa1cd9_e6af10a5 PS1, Line 191: /** : * \brief Pre call to RAM stage main() : * : * POSTed right before RAM stage main() is called from c_start.S : */ : #define POST_PRE_HARDWAREMAIN 0x7c : : /** : * \brief Entry into coreboot in RAM stage main() : * : * This is the first call in hardwaremain.c. If this code is POSTed, then : * ramstage has successfully loaded and started executing. : */ : #define POST_ENTRY_RAMSTAGE 0x80 Just a thought: Should POST_PRE_HARDWAREMAIN be 0x6e and POST_ENTRY_RAMSTAGE 0x6f so that the post codes appear in an increasing fashion? Does that even matter? -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: add check for maximum table size
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52897 ) Change subject: soc/amd/common/fsp/fsp-acpi: add check for maximum table size ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Gerrit-Change-Number: 52897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 18:38:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: add check for maximum table size
by Jason Glenesk (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52897 ) Change subject: soc/amd/common/fsp/fsp-acpi: add check for maximum table size ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: good catch -- To view, visit https://review.coreboot.org/c/coreboot/+/52897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Gerrit-Change-Number: 52897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 18:34:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: add check for maximum table size
by Felix Held (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52897 ) Change subject: soc/amd/common/fsp/fsp-acpi: add check for maximum table size ...................................................................... soc/amd/common/fsp/fsp-acpi: add check for maximum table size If the ACPI table size in the HOB data header is larger than the maximum HOB payload, don't add the table at all and print an error instead, since in this case the memcpy would read past the end of the HOB data structure. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 --- M src/soc/amd/common/fsp/fsp-acpi.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52897/1 diff --git a/src/soc/amd/common/fsp/fsp-acpi.c b/src/soc/amd/common/fsp/fsp-acpi.c index b530688..f92d571 100644 --- a/src/soc/amd/common/fsp/fsp-acpi.c +++ b/src/soc/amd/common/fsp/fsp-acpi.c @@ -28,6 +28,12 @@ return current; } + if (data->table_size_in_bytes > sizeof(data->hob_payload)) { + printk(BIOS_ERR, "AGESA %s ACPI table size larger than maximum HOB payload " + "size.\n", name); + return current; + } + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); memcpy(table, data->hob_payload, data->table_size_in_bytes); -- To view, visit https://review.coreboot.org/c/coreboot/+/52897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Gerrit-Change-Number: 52897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52896 ) Change subject: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality ...................................................................... soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality This function will be reused in Cezanne, so move it from the Picasso directory to the common FSP integration code. TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b --- M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp-acpi.c M src/soc/amd/picasso/agesa_acpi.c 4 files changed, 46 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/52896/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 215d668..eec5a3f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -56,4 +56,7 @@ unsigned long acpi_fill_madt_irqoverride(unsigned long current); void acpi_fill_root_complex_tom(const struct device *device); +uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current); + #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index 5523876..3ba6ea5 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -1,4 +1,5 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += fsp_reset.c ramstage-y += fsp_reset.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c endif # CONFIG_PLATFORM_USES_FSP2_0 diff --git a/src/soc/amd/common/fsp/fsp-acpi.c b/src/soc/amd/common/fsp/fsp-acpi.c new file mode 100644 index 0000000..b530688 --- /dev/null +++ b/src/soc/amd/common/fsp/fsp-acpi.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <console/console.h> +#include <fsp/util.h> +#include <string.h> +#include <types.h> + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; /* maximum payload size */ +} __packed; + +uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index b5982c8..5122be5 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -6,12 +6,12 @@ #include <console/console.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> -#include <fsp/util.h> #include <FspGuids.h> #include <soc/acpi.h> #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <amdblocks/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> @@ -20,38 +20,6 @@ #include <stdlib.h> #include <arch/mmio.h> -struct amd_fsp_acpi_hob_info { - uint32_t table_size_in_bytes; - uint8_t total_hobs_for_table; - uint8_t sequence_number; - uint16_t reserved; - uint16_t hob_payload[0xffc8]; -} __packed; - -static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, - uintptr_t current) -{ - const struct amd_fsp_acpi_hob_info *data; - void *table = (void *)current; - size_t hob_size; - - data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); - if (!data) { - printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); - return current; - } - - printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); - - memcpy(table, data->hob_payload, data->table_size_in_bytes); - - current += data->table_size_in_bytes; - acpi_add_table(rsdp, table); - current = acpi_align_current(current); - - return current; -} - unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -1033,7 +1001,7 @@ current += crat->header.length; acpi_add_table(rsdp, crat); - current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ current = ALIGN(current, 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/52896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Gerrit-Change-Number: 52896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Subrata Banik (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... Patch Set 1: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52893/comment/51370995_fba70382 PS1, Line 182: 0x79 > I think it is okay. […] Sure Furquan, Please let me know https://review.coreboot.org/c/coreboot/+/52895/1 if you would like to add more details ? -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 04 May '21

04 May '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... include/console: Fix duplicate entry of postcode 0x79 Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x7c to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/c_start.S M src/include/console/post_codes.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52895/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 19532d8..e515dbc 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -89,7 +89,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + post_code(POST_PRE_HARDWAREMAIN) /* post 7c */ andl $0xFFFFFFF0, %esp diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 69047f8..5af6734 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -175,13 +175,6 @@ #define POST_BS_WRITE_TABLES 0x79 /** - * \brief Pre call to RAM stage main() - * - * POSTed right before RAM stage main() is called from c_start.S - */ -#define POST_PRE_HARDWAREMAIN 0x79 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -196,6 +189,13 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Pre call to RAM stage main() + * + * POSTed right before RAM stage main() is called from c_start.S + */ +#define POST_PRE_HARDWAREMAIN 0x7c + +/** * \brief Entry into coreboot in RAM stage main() * * This is the first call in hardwaremain.c. If this code is POSTed, then -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... Patch Set 1: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52893/comment/443e6550_6828c9d2 PS1, Line 182: 0x79 > Yes, i was adding 0x7c for POST_PRE_HARDWAREMAIN, submitting the CL, hopes that fine, because we hav […] I think it is okay. Only thing I would be worried about is if anyone is using any scripts/tests that look for that particular post code. But, then those scripts would really be checking for post code at incorrect point in boot. Let's make sure that the detail is properly captured in the commit message of the new CL so that people understand the impact of the change. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 18:30:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021