coreboot-gerrit May 2021

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Change in coreboot[master]: mb/intel/adlrvp_m: Disable Type-C xDCI
by Bernardo Perez Priego (Code Review) 04 May '21

04 May '21

Attention is currently required from: Anil Kumar K, Selma Bensaid, Bernardo Perez Priego. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Selma Bensaid, Sukumar Ghorai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52744 to look at the new patch set (#2). Change subject: mb/intel/adlrvp_m: Disable Type-C xDCI ...................................................................... mb/intel/adlrvp_m: Disable Type-C xDCI Disabling this pci 0d.1 device since it is not required. TEST= Boot to OS. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be --- M src/mainboard/intel/adlrvp/devicetree_m.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52744/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be Gerrit-Change-Number: 52744 Gerrit-PatchSet: 2 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUID
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52903 ) Change subject: vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUID ...................................................................... vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUID Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I531c8e8d0ee2aa72b51cba59e09e7a7d253da4f9 --- M src/vendorcode/amd/fsp/cezanne/FspGuids.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/52903/1 diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h index 7f7a91d..ca8cfc5 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspGuids.h +++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h @@ -13,4 +13,8 @@ GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \ 0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8) +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + #endif /* __FSP_GUIDS__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I531c8e8d0ee2aa72b51cba59e09e7a7d253da4f9 Gerrit-Change-Number: 52903 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] soc/amd/cezanne/agesa_acpi: add add_agesa_fsp_acpi_table call
by Felix Held (Code Review) 04 May '21

04 May '21

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Change in coreboot[master]: soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables
by Felix Held (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52902 ) Change subject: soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables ...................................................................... soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables This function will be used to add some SSDTs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26 --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/agesa_acpi.c M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/include/soc/acpi.h 4 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52902/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index e51a616..ebdad45 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += i2c.c ramstage-y += acpi.c +ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric.c diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c new file mode 100644 index 0000000..8084e4d --- /dev/null +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <types.h> + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + return current; +} diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 8625bd7..625f46c 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> @@ -79,6 +80,8 @@ static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h index 1b1d2fb..ab90c96 100644 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -3,6 +3,11 @@ #ifndef AMD_CEZANNE_ACPI_H #define AMD_CEZANNE_ACPI_H +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <device/device.h> +#include <stdint.h> + #define ACPI_SCI_IRQ 9 /* RTC Registers */ @@ -10,4 +15,7 @@ #define RTC_ALT_CENTURY 0x32 #define RTC_CENTURY 0x48 +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + #endif /* AMD_CEZANNE_ACPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26 Gerrit-Change-Number: 52902 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/agesa_acpi: add comment to add_agesa_fsp_acpi_table call
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52901 ) Change subject: soc/amd/picasso/agesa_acpi: add comment to add_agesa_fsp_acpi_table call ...................................................................... soc/amd/picasso/agesa_acpi: add comment to add_agesa_fsp_acpi_table call Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I409993dcecd38bd2ad603ba467b299a6eab177ab --- M src/soc/amd/picasso/agesa_acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/52901/1 diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index a8ce780..abac9c1 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1002,6 +1002,7 @@ current += crat->header.length; acpi_add_table(rsdp, crat); + /* add ALIB SSDT from HOB */ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I409993dcecd38bd2ad603ba467b299a6eab177ab Gerrit-Change-Number: 52901 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52896 ) Change subject: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/amd/common/fsp/fsp-acpi.c: https://review.coreboot.org/c/coreboot/+/52896/comment/05b12029_b80d78c0 PS1, Line 18: add_agesa_fsp_acpi_table > this is a generic function to add a ssdt from a hob. […] ah, the GUID is what describes the table. Thanks for the clarification. -- To view, visit https://review.coreboot.org/c/coreboot/+/52896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Gerrit-Change-Number: 52896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 19:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/agesa_acpi: add missing device/device.h include
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52899 ) Change subject: soc/amd/picasso/agesa_acpi: add missing device/device.h include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7892cf680661253f74c3e291f5e9fb372e1d4ce3 Gerrit-Change-Number: 52899 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 19:13:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Furquan Shaikh (Code Review) 04 May '21

04 May '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Let's see what others think. -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 19:13:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Patrick Rudolph (Code Review) 04 May '21

04 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Arthur Heymans, Morgan Jang. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Gerrit-Change-Number: 52898 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 04 May 2021 19:08:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Update AMDFW config file
by Martin Roth (Code Review) 04 May '21

04 May '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52900 ) Change subject: mb/google/mancomb: Update AMDFW config file ...................................................................... mb/google/mancomb: Update AMDFW config file Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for the LPDDR4 version. This changes to use SODIMMS. Further changes may be needed for platform customization, so I put the config file in variants/baseboard instead of the root mancomb directory. BUG=b:187094481 TEST=Build only Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe --- M src/mainboard/google/mancomb/Kconfig A src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg 2 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52900/1 diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 4ed29cd..d114f0e 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -63,6 +63,10 @@ hex default 0x50 +config AMDFW_CONFIG_FILE + string + default "src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg" + config EFS_SPI_READ_MODE int default 0 if EM100 # Normal read mode diff --git a/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg b/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg new file mode 100644 index 0000000..50b2edc --- /dev/null +++ b/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg @@ -0,0 +1,40 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN.csbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin + +# BDT +PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin -- To view, visit https://review.coreboot.org/c/coreboot/+/52900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Gerrit-Change-Number: 52900 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021