coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/dedede/var/cret: Modify reset setting for touchscreen
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52727 ) Change subject: mb/google/dedede/var/cret: Modify reset setting for touchscreen ...................................................................... mb/google/dedede/var/cret: Modify reset setting for touchscreen Modify reset pin setting to ACPI_GPIO_OUTPUT_ACTIVE_LOW for ELAN and Weida touchscreen. BUG=b:180547621 BRANCH=dedede TEST=Build the cret board and touchscreen is workable. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I912fe8a0e18a4c3527fb8587592b855c93b12406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52727 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 0cf3bdf..512a956 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -114,7 +114,7 @@ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "generic.reset_delay_ms" = "20" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" @@ -132,7 +132,7 @@ register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "reset_delay_ms" = "20" register "reset_off_delay_ms" = "2" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" -- To view, visit https://review.coreboot.org/c/coreboot/+/52727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I912fe8a0e18a4c3527fb8587592b855c93b12406 Gerrit-Change-Number: 52727 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*/Kconfig: Drop select USE_OPTION_TABLE
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52855 ) Change subject: mb/*/Kconfig: Drop select USE_OPTION_TABLE ...................................................................... mb/*/Kconfig: Drop select USE_OPTION_TABLE Only 4 mainboards selected to use the option table. Use the same default on all boards. Change-Id: Ia9ef88d5158a2b43f843c26b5b366a899dad8788 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbook21/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/lenovo/x60/Kconfig 4 files changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 9eb06ff..5d8f626 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -15,7 +15,6 @@ select INTEL_INT15 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select USE_OPTION_TABLE select I945_LVDS config MAINBOARD_DIR diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index af723a3..4e9583c 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -32,12 +32,4 @@ string default "H81M-HDS" -# -# Since this is a desktop board, the assumption is made that most users -# would want CMOS configuration enabled by default. -# -config USE_OPTION_TABLE - bool - default y - endif diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 78948b2..365043c 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -7,7 +7,6 @@ select FORCE_AM1_SOCKET_SUPPORT select GFXUMA select HAVE_OPTION_TABLE - select USE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 8397835..3a82179 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -21,7 +21,6 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select USE_OPTION_TABLE select DRIVERS_LENOVO_WACOM select I945_LVDS select INTEL_GMA_HAVE_VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/52855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ef88d5158a2b43f843c26b5b366a899dad8788 Gerrit-Change-Number: 52855 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Configure Pen Detect device
by Karthik Ramasubramanian (Code Review) 04 May '21

04 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Mathew King. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52906 ) Change subject: mb/google/guybrush: Configure Pen Detect device ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52906/comment/4255a421_1ada1705 PS1, Line 20: suspended > Can you verify you can do a second S0i3 cycle after waking with the pen. Yes, with the pen eject switch released (pen ejected), system can enter S0i3. Then pressing the switch (pen insert) does not wake the system. Then releasing the switch again (pen eject) system wakes again. -- To view, visit https://review.coreboot.org/c/coreboot/+/52906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Gerrit-Change-Number: 52906 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 21:13:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/cezanne: Add support for AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
by Felix Held (Code Review) 04 May '21

04 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52869 ) Change subject: vc/amd/fsp/cezanne: Add support for AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h: https://review.coreboot.org/c/coreboot/+/52869/comment/87a8e32a_f0892ffb PS1, Line 38: static inline const struct pcie_routing_info *get_pcie_routing_info(unsigned int devfn) i wouldn't put the two functions here in a header in the vendorcode directory, but move them to the soc directory https://review.coreboot.org/c/coreboot/+/52869/comment/0175b81b_5c96de7e PS1, Line 43: fsp_find_extension_hob_by_guid since this function call is rather expensive in terms of time, i wouldn't do the call for every irq number calculation. maybe use a static pointer and only do the call if it's NULL. at least for the acpi table generation that was moved from fsp to native coreboot code for picasso it was faster to generate the ssdt in coreboot and just ignore the hob than finding and copying the hob and that was just one call -- To view, visit https://review.coreboot.org/c/coreboot/+/52869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Gerrit-Change-Number: 52869 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 21:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Configure Pen Detect device
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Mathew King, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52906 ) Change subject: mb/google/guybrush: Configure Pen Detect device ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52906/comment/9b2a1b1f_a0229838 PS1, Line 20: suspended Can you verify you can do a second S0i3 cycle after waking with the pen. -- To view, visit https://review.coreboot.org/c/coreboot/+/52906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Gerrit-Change-Number: 52906 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 20:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call
by Felix Held (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52907 ) Change subject: [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I'd say that we should write those registers even though at least some registers have been set up by the psp; just to be sure that they really end up having the values we expect them to have -- To view, visit https://review.coreboot.org/c/coreboot/+/52907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224b99b1aace3e4220bccec836efee0130ebbfdb Gerrit-Change-Number: 52907 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 04 May 2021 20:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src: Retype option API to use unsigned integers
by Felix Singer (Code Review) 04 May '21

04 May '21

Attention is currently required from: Damien Zammit, Tristan Corrick, Angel Pons, Alexander Couzens, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52672 ) Change subject: src: Retype option API to use unsigned integers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Gerrit-Change-Number: 52672 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 20:33:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call
by Felix Held (Code Review) 04 May '21

04 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52907 ) Change subject: [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call ...................................................................... [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call Before this can be merged, the mainboard's devicetrees need to be updated to set common_config.spi_config to working value, since the frequencies default to 66MHz in non-EM100 mode which might be too much. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I224b99b1aace3e4220bccec836efee0130ebbfdb --- M src/soc/amd/cezanne/early_fch.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/52907/1 diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index fdfa17a..2da338f 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -36,6 +36,7 @@ void fch_pre_init(void) { lpc_early_init(); + fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/52907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224b99b1aace3e4220bccec836efee0130ebbfdb Gerrit-Change-Number: 52907 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Configure Pen Detect device
by Karthik Ramasubramanian (Code Review) 04 May '21

04 May '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52906 ) Change subject: mb/google/guybrush: Configure Pen Detect device ...................................................................... mb/google/guybrush: Configure Pen Detect device Pen Detect GPIO is exported through GPIO keys driver to the kernel so that stylus tools is popped on pen eject event. Hence enable the GPIO keys driver and configure the devicetree. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is added to the ACPI SSDT table. Ensure that the Pen Eject events are detected. Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1620159356.243180, -------------- SYN_REPORT ------------ Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Ensure that when the device is suspended, it wake on Pen Eject event and does not wake on Pen Insert event. Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/52906/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 51ac55d..8c23cf0 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -12,6 +12,7 @@ select DISABLE_KEYBOARD_RESET_PIN select DISABLE_SPI_FLASH_ROM_SHARING select DRIVERS_AMD_I2S_MACHINE_DEV + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_UART_ACPI diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 53e821e..416d058 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -84,6 +84,21 @@ end end # I2C0 + device ref i2c_1 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end + end # I2C1 + device ref i2c_2 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/52906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Gerrit-Change-Number: 52906 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] soc/amd/cezanne: add GNB IOAPIC support
by Felix Held (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52905 to look at the new patch set (#2). Change subject: [UNTESTED] soc/amd/cezanne: add GNB IOAPIC support ...................................................................... [UNTESTED] soc/amd/cezanne: add GNB IOAPIC support To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/root_complex.c 4 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52905/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Gerrit-Change-Number: 52905 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021