coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/guybrush: Configure wake resource for WiFi
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: Raul Rangel, Martin Roth, Furquan Shaikh, Mathew King. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52908 ) Change subject: mb/google/guybrush: Configure wake resource for WiFi ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52908/comment/f86f4e3e_fd2208c9 PS1, Line 13: is added to SSDT. I … [View More]

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by Felix Singer (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/… [View More]

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Change in coreboot[master]: mb/google/guybrush: Configure wake resource for WiFi
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52908 ) Change subject: mb/google/guybrush: Configure wake resource for WiFi ...................................................................... mb/google/guybrush: Configure wake resource for WiFi In order to support wake on WLAN events, configure the wake resource. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource is added to SSDT. Device (\… [View More]_SB.PCI0.GP20.WF00) { Name (_UID, 0x38B82CBC) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.GP20.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x08, 0x03 }) } Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52908/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 51ac55d..84c8285 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -15,6 +15,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_UART_ACPI + select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3097425..bdd18c7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -53,7 +53,12 @@ GPIO_I2C2_SCL | GPIO_I2C3_SCL" device domain 0 on - device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_0 on + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end # WLAN device ref gpp_bridge_1 on end # SD device ref gpp_bridge_2 on end # WWAN device ref gpp_bridge_3 on end # NVMe -- To view, visit https://review.coreboot.org/c/coreboot/+/52908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288 Gerrit-Change-Number: 52908 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: inteltool: add initial support for Emmits Burg PCH
by Maxim Polyakov (Code Review) 05 May '21

05 May '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52864 ) Change subject: inteltool: add initial support for Emmits Burg PCH ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52864 To unsubscribe, or for … [View More]

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Change in coreboot[master]: inteltool: add initial suppot for Sapphire Rapids Scalable Processor
by Maxim Polyakov (Code Review) 05 May '21

05 May '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52863 ) Change subject: inteltool: add initial suppot for Sapphire Rapids Scalable Processor ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52863 To … [View More]

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Change in coreboot[master]: util/intelp2m: Set GO111MODULE environment parameter explicitly
by Maxim Polyakov (Code Review) 04 May '21

04 May '21

Attention is currently required from: Arthur Heymans. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52862 ) Change subject: util/intelp2m: Set GO111MODULE environment parameter explicitly ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings … [View More]

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Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in ...
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

Attention is currently required from: Furquan Shaikh, Kane Chen, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52873 ) Change subject: soc/intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in sleep smi ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52873/comment/37ca4be4_be91341f PS4, Line 7: soc/… [View More]intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in sleep smi : : We found system hang if the shutdown is triggered before fsps. : This is due to the io decode enable on pmc is disabled by : busmaster_disable_on_bus function. : Hence, the slp_en on acpi pm1_cnt register doesn't succeed. : So this change skip pmc bus disable before shutdown. : : The reason issue is not reproduced after fsps is beacause pmc pci : device is hidden after fsps. : That's why busmaster_disable_on_bus won't clear io deocde on pmc device. suggestion: ``` soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster If a power button SMI is triggered between where it is currently enabled and before FSP-S exits, when the SMI handler disables bus mastering for all devices, it inadvertently also disables the PMC's I/O decoding, so the register write to actually go into S5 does not succeed, and the system hangs. This can be solved by skipping the PMC when disabling bus mastering in the SMI handler, for which a callback, smihandler_soc_disable_busmaster is provided. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/52873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Gerrit-Change-Number: 52873 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 21:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
by Tim Wawrzynczak (Code Review) 04 May '21

04 May '21

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Change in coreboot[master]: src/cpu/x86/smm: remove debug message; not thread safe
by Rocky Phagura (Code Review) 04 May '21

04 May '21

Attention is currently required from: David Hendricks, Angel Pons, Arthur Heymans. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52518 ) Change subject: src/cpu/x86/smm: remove debug message; not thread safe ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52518/comment/79e3a185_6bd79b26 PS3, Line 16: . > one period too many? Done -- … [View More]

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Change in coreboot[master]: src/cpu/x86/smm: remove debug message; not thread safe
by Rocky Phagura (Code Review) 04 May '21

04 May '21

Attention is currently required from: David Hendricks, Rocky Phagura, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Jonathan Zhang, David Hendricks, Rocky Phagura, Angel Pons, Arthur Heymans, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52518 to look at the new patch set (#4). Change subject: src/cpu/x86/smm: remove debug message; not thread safe ...................................................................... … [View More]

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coreboot-gerrit May 2021