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Change subject: util/intelp2m: Set GO111MODULE environment parameter explicitly
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52873 )
Change subject: soc/intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in sleep smi
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52873/comment/37ca4be4_be91341f
PS4, Line 7: soc/intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in sleep smi
:
: We found system hang if the shutdown is triggered before fsps.
: This is due to the io decode enable on pmc is disabled by
: busmaster_disable_on_bus function.
: Hence, the slp_en on acpi pm1_cnt register doesn't succeed.
: So this change skip pmc bus disable before shutdown.
:
: The reason issue is not reproduced after fsps is beacause pmc pci
: device is hidden after fsps.
: That's why busmaster_disable_on_bus won't clear io deocde on pmc device.
suggestion:
```
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently
enabled and before FSP-S exits, when the SMI handler disables
bus mastering for all devices, it inadvertently also disables
the PMC's I/O decoding, so the register write to actually go into
S5 does not succeed, and the system hangs.
This can be solved by skipping the PMC when disabling bus
mastering in the SMI handler, for which a callback,
smihandler_soc_disable_busmaster is provided.
```
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52874 )
Change subject: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/52874/comment/8cfd266c_5e5ec091
PS5, Line 101: /*
: * Now that all APs have been relocated as well as the BSP let SMIs
: * start flowing.
: */
Can you please update all of these comments as to the reason why the `_no_powrbtn` variant is used here?
File src/soc/intel/alderlake/pmc.c:
https://review.coreboot.org/c/coreboot/+/52874/comment/400c5a5d_fce2dc5e
PS5, Line 148: (FSPS)
nit: space after `(`, also please spell it `FSP-S`
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Hello build bot (Jenkins), Nico Huber, Jonathan Zhang, David Hendricks, Rocky Phagura, Angel Pons, Arthur Heymans, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52518
to look at the new patch set (#4).
Change subject: src/cpu/x86/smm: remove debug message; not thread safe
......................................................................
src/cpu/x86/smm: remove debug message; not thread safe
This patch removes a call to console_init() and debug print message since
the code is not thread safe. This prevents system hangs (soft hangs)
while in SMM if user drops in a new SOC with more cores or another
socket or as a result of bad configuration. Console is already
initialized after the lock has been acquired so this does not affect any
other functionality.
Tested on DeltaLake mainboard with SMM enabled and 52 CPU threads.
Change-Id: I7e8af35d1cde78b327144b6a9da528ae7870e874
Signed-off-by: Rocky Phagura <rphagura(a)fb.com>
---
M src/cpu/x86/smm/smm_module_handler.c
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/52518/4
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52853 )
Change subject: security/vboot: Include fspt.bin in the RO region only
......................................................................
security/vboot: Include fspt.bin in the RO region only
fspt.bin is run before verstage so it is of no use in RW_A/B.
Change-Id: I6fe29793fa638312c8b275b6fa8662df78b3b2bd
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52853
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
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---
M src/security/vboot/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Aaron Durbin: Looks good to me, approved
Michał Żygowski: Looks good to me, approved
diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc
index cecaa2d..668d3d9 100644
--- a/src/security/vboot/Makefile.inc
+++ b/src/security/vboot/Makefile.inc
@@ -187,6 +187,7 @@
cmos.default \
intel_fit \
intel_fit_ts \
+ fspt.bin \
$(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \
,$(1)),COREBOOT,\
$(if $(filter \
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