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Change subject: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
......................................................................
vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
This HOB describes the PCI routing table. It will be consumed by
coreboot to generate the _PRT ACPI object.
BUG=b:184766519, b:184766197
TEST=Build guybrush
Cq-Depend: chrome-internal:3794981
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db
---
M src/vendorcode/amd/fsp/cezanne/FspGuids.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52869/2
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names
......................................................................
soc/amd/cezanne: Generate PCI GPP ACPI names
We can generate the names, so there is no need to hard code a table.
This will make the code more generic so it can be reused with picasso in
the future.
BUG=b:184766519
TEST=Dump guybrush ACPI table and verify it looks correct.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11
---
M src/soc/amd/cezanne/pcie_gpp.c
1 file changed, 9 insertions(+), 31 deletions(-)
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Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52909 )
Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
The counterpart to the amd-fsp code
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52851 )
Change subject: mb/google/dedede/var/magolor: Select elan hidi2c address based on SSFC value
......................................................................
Patch Set 2:
(1 comment)
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PS2:
Leave some discussion in the issue tracker first.
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Change subject: mb/google/guybrush: Configure wake resource for WiFi
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52908/comment/f86f4e3e_fd2208c9
PS1, Line 13: is added to SSDT.
I am trying to wake on WiFi. Unfortunately the device is not waking up. Is there anything that I am missing?
GPIO_2 is mapped to GEVENT_8.
GPIO_2 is configured as here: https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he…
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 )
Change subject: [RFC] device: Introduce new method for setting device states
......................................................................
Patch Set 20:
(1 comment)
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/52493/comment/4815f56f_b5cfed8c
PS13, Line 461: if (!xdci_can_enable())
: params->XdciEnable = 0;
> Felix, what do you think?
reopened
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52908 )
Change subject: mb/google/guybrush: Configure wake resource for WiFi
......................................................................
mb/google/guybrush: Configure wake resource for WiFi
In order to support wake on WLAN events, configure the wake resource.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource
is added to SSDT.
Device (\_SB.PCI0.GP20.WF00)
{
Name (_UID, 0x38B82CBC) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.GP20.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x08,
0x03
})
}
Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52908/1
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 51ac55d..84c8285 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -15,6 +15,7 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_UART_ACPI
+ select DRIVERS_WIFI_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 3097425..bdd18c7 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -53,7 +53,12 @@
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device domain 0 on
- device ref gpp_bridge_0 on end # WLAN
+ device ref gpp_bridge_0 on
+ chip drivers/wifi/generic
+ register "wake" = "GEVENT_8"
+ device pci 00.0 on end
+ end
+ end # WLAN
device ref gpp_bridge_1 on end # SD
device ref gpp_bridge_2 on end # WWAN
device ref gpp_bridge_3 on end # NVMe
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