coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/cezanne: Populate PCI_INTR registers
by Raul Rangel (Code Review) 04 May '21

04 May '21

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Change in coreboot[master]: soc/amd/common/fsp/pci: Implement populate_pirq_data
by Raul Rangel (Code Review) 04 May '21

04 May '21

1 0

Change in coreboot[master]: soc/amd/{picasso/common}: Move populate_pirq_data to common
by Raul Rangel (Code Review) 04 May '21

04 May '21

1 0

Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52911 ) Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 --- A src/soc/amd/common/fsp/pci/Kconfig A src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/pci_routing_info.c A src/soc/amd/common/fsp/pci/pci_routing_info.h 4 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52911/1 diff --git a/src/soc/amd/common/fsp/pci/Kconfig b/src/soc/amd/common/fsp/pci/Kconfig new file mode 100644 index 0000000..358da0e --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_FSP_PCI + bool + select SOC_AMD_COMMON_BLOCK_PCI + help + This option builds functions to generate PCI _PRT tables and to + program PCI interrupt routing. diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc new file mode 100644 index 0000000..cc1377a --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y) + +ramstage-y += pci_routing_info.c + +endif # CONFIG_SOC_AMD_COMMON_FSP_PCI diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c new file mode 100644 index 0000000..c600cb9 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "pci_routing_info.h" +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <types.h> + +enum pcie_swizzle_pin { + PIN_A, + PIN_B, + PIN_C, + PIN_D, +}; + +static const uint8_t pcie_swizzle_table[][4] = { + {PIN_A, PIN_B, PIN_C, PIN_D}, + {PIN_B, PIN_C, PIN_D, PIN_A}, + {PIN_C, PIN_D, PIN_A, PIN_B}, + {PIN_D, PIN_A, PIN_B, PIN_C}, +}; + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + const struct pci_routing_info *routing_table; + size_t hob_size = 0; + + routing_table = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b, + &hob_size); + + if (routing_table == NULL || hob_size == 0) { + printk(BIOS_ERR, "Couldn't find PCIe routing HOB.\n"); + return NULL; + } + + *entries = hob_size / sizeof(*routing_table); + + return routing_table; +} + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn) +{ + const struct pci_routing_info *routing_info; + size_t entries = 0; + + routing_info = get_pci_routing_table(&entries); + + if (!routing_info) + return NULL; + + for (size_t i = 0; i < entries; ++i, ++routing_info) + if (routing_info->devfn == devfn) + return routing_info; + + printk(BIOS_ERR, "Failed to find PCIe routing info for dev: %#x, fn: %#x\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + return NULL; +} + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, + unsigned int pin) +{ + unsigned int irq; + + if (routing_info->swizzle > ARRAY_SIZE(pcie_swizzle_table)) + die("%s: swizzle %u out of bounds\n", __func__, routing_info->swizzle); + + if (pin > ARRAY_SIZE(pcie_swizzle_table[routing_info->swizzle])) + die("%s: pin %u out of bounds\n", __func__, pin); + + irq = routing_info->group * 4; + irq += pcie_swizzle_table[routing_info->swizzle][pin]; + + return irq; +} diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.h b/src/soc/amd/common/fsp/pci/pci_routing_info.h new file mode 100644 index 0000000..46ce6a4 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_COMMON_FSP_PCI_ROUTING_H_ +#define _AMD_COMMON_FSP_PCI_ROUTING_H_ + +#include <types.h> + +/** + * Each PCI bridge has its INTx lines routed to one of the GNB IOAPIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. + **/ +struct pci_routing_info { + uint8_t devfn; + uint8_t group; + uint8_t swizzle; + uint8_t irq; +}; + +const struct pci_routing_info *get_pci_routing_table(size_t *entries); + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn); + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); + +#endif /* _AMD_COMMON_FSP_PCI_ROUTING_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Add Kconfig/Makefile support for common/fsp/*
by Raul Rangel (Code Review) 04 May '21

04 May '21

1 0

Change in coreboot[master]: soc/amd/cezanne: Generate PCI GPP ACPI names
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52870 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names ...................................................................... soc/amd/cezanne: Generate PCI GPP ACPI names We can generate the names, so there is no need to hard code a table. This will make the code more generic so it can be reused with picasso in the future. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 --- M src/soc/amd/cezanne/pcie_gpp.c 1 file changed, 9 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52870/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Gerrit-Change-Number: 52870 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian. Hello build bot (Jenkins), Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52869 to look at the new patch set (#2). Change subject: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID ...................................................................... vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID This HOB describes the PCI routing table. It will be consumed by coreboot to generate the _PRT ACPI object. BUG=b:184766519, b:184766197 TEST=Build guybrush Cq-Depend: chrome-internal:3794981 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db --- M src/vendorcode/amd/fsp/cezanne/FspGuids.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52869/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Gerrit-Change-Number: 52869 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
by Julian Schroeder (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Marshall Dawson, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52909 ) Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: The counterpart to the amd-fsp code -- To view, visit https://review.coreboot.org/c/coreboot/+/52909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d Gerrit-Change-Number: 52909 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 22:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
by Julian Schroeder (Code Review) 04 May '21

04 May '21

Julian Schroeder has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52909 ) Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp ...................................................................... src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp Added sh_oem_usb_config to match amd-fsp FspmUpd.h. This is needed to enable USBC port muxes in Cezanne. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/52909/1 diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f01af85..bcc54a9 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -107,8 +107,9 @@ /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; - /** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41]; - /** Offset 0x0500**/ uint16_t UpdTerminator; + /** Offset 0x04D7**/ uint8_t sh_oem_usb_config[100]; + /** Offset 0x053B**/ uint8_t UnusedUpdSpace0[197]; + /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/52909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d Gerrit-Change-Number: 52909 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select elan hidi2c address based on SSF...
by Marco Chen (Code Review) 04 May '21

04 May '21

Attention is currently required from: David Wu, Henry Sun. Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52851 ) Change subject: mb/google/dedede/var/magolor: Select elan hidi2c address based on SSFC value ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Leave some discussion in the issue tracker first. -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 22:51:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021