Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52911 )
Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ......................................................................
soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.
BUG=b:184766519, b:184766197 TEST=Build guybrush
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 --- A src/soc/amd/common/fsp/pci/Kconfig A src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/pci_routing_info.c A src/soc/amd/common/fsp/pci/pci_routing_info.h 4 files changed, 115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52911/1
diff --git a/src/soc/amd/common/fsp/pci/Kconfig b/src/soc/amd/common/fsp/pci/Kconfig new file mode 100644 index 0000000..358da0e --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_FSP_PCI + bool + select SOC_AMD_COMMON_BLOCK_PCI + help + This option builds functions to generate PCI _PRT tables and to + program PCI interrupt routing. diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc new file mode 100644 index 0000000..cc1377a --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y) + +ramstage-y += pci_routing_info.c + +endif # CONFIG_SOC_AMD_COMMON_FSP_PCI diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c new file mode 100644 index 0000000..c600cb9 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "pci_routing_info.h" +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <types.h> + +enum pcie_swizzle_pin { + PIN_A, + PIN_B, + PIN_C, + PIN_D, +}; + +static const uint8_t pcie_swizzle_table[][4] = { + {PIN_A, PIN_B, PIN_C, PIN_D}, + {PIN_B, PIN_C, PIN_D, PIN_A}, + {PIN_C, PIN_D, PIN_A, PIN_B}, + {PIN_D, PIN_A, PIN_B, PIN_C}, +}; + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + const struct pci_routing_info *routing_table; + size_t hob_size = 0; + + routing_table = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b, + &hob_size); + + if (routing_table == NULL || hob_size == 0) { + printk(BIOS_ERR, "Couldn't find PCIe routing HOB.\n"); + return NULL; + } + + *entries = hob_size / sizeof(*routing_table); + + return routing_table; +} + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn) +{ + const struct pci_routing_info *routing_info; + size_t entries = 0; + + routing_info = get_pci_routing_table(&entries); + + if (!routing_info) + return NULL; + + for (size_t i = 0; i < entries; ++i, ++routing_info) + if (routing_info->devfn == devfn) + return routing_info; + + printk(BIOS_ERR, "Failed to find PCIe routing info for dev: %#x, fn: %#x\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + return NULL; +} + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, + unsigned int pin) +{ + unsigned int irq; + + if (routing_info->swizzle > ARRAY_SIZE(pcie_swizzle_table)) + die("%s: swizzle %u out of bounds\n", __func__, routing_info->swizzle); + + if (pin > ARRAY_SIZE(pcie_swizzle_table[routing_info->swizzle])) + die("%s: pin %u out of bounds\n", __func__, pin); + + irq = routing_info->group * 4; + irq += pcie_swizzle_table[routing_info->swizzle][pin]; + + return irq; +} diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.h b/src/soc/amd/common/fsp/pci/pci_routing_info.h new file mode 100644 index 0000000..46ce6a4 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_COMMON_FSP_PCI_ROUTING_H_ +#define _AMD_COMMON_FSP_PCI_ROUTING_H_ + +#include <types.h> + +/** + * Each PCI bridge has its INTx lines routed to one of the GNB IOAPIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. + **/ +struct pci_routing_info { + uint8_t devfn; + uint8_t group; + uint8_t swizzle; + uint8_t irq; +}; + +const struct pci_routing_info *get_pci_routing_table(size_t *entries); + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn); + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); + +#endif /* _AMD_COMMON_FSP_PCI_ROUTING_H_ */