coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards
by Aaron Durbin (Code Review) 04 May '21

04 May '21

Attention is currently required from: Aseda Aboagye. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52920 ) Change subject: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/52920/comment/563f39fb_88e46be6 PS1, Line 167: select TPM20_CREATE_FWMP Doesn't this selection need to be under another config? Basically move this to line 41 or 42. Btw, I *think* Andrey wanted to do this for all Chrome OS devices going forward. So we may want to just do it unconditionally for all Chrome OS devices going forward. -- To view, visit https://review.coreboot.org/c/coreboot/+/52920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c49f2018baa17df8c932b7a7d7f1aec28749ff2 Gerrit-Change-Number: 52920 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 23:49:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: chromeos/Kconfig: Add TPM20_CREATE_FWMP
by Aseda Aboagye (Code Review) 04 May '21

04 May '21

Attention is currently required from: Aaron Durbin. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52919 ) Change subject: chromeos/Kconfig: Add TPM20_CREATE_FWMP ...................................................................... Patch Set 1: (1 comment) File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/52919/comment/c40b1729_84b6db5d PS1, Line 246: if (rv == TPM_E_NV_DEFINED) { > Is this our expected return value? If so, could you please add a comment indicating expectations an […] Negative. This scenario should be rare (e.g. we define the FWMP space, but lose power before setting the firmware space). However, I can add this brief description to this portion. -- To view, visit https://review.coreboot.org/c/coreboot/+/52919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Gerrit-Change-Number: 52919 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 04 May 2021 23:46:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: chromeos/Kconfig: Add TPM20_CREATE_FWMP
by Aaron Durbin (Code Review) 04 May '21

04 May '21

Attention is currently required from: Aseda Aboagye. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52919 ) Change subject: chromeos/Kconfig: Add TPM20_CREATE_FWMP ...................................................................... Patch Set 1: (1 comment) File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/52919/comment/b094ab81_134e3b97 PS1, Line 246: if (rv == TPM_E_NV_DEFINED) { Is this our expected return value? If so, could you please add a comment indicating expectations and flow of the creation of this space? -- To view, visit https://review.coreboot.org/c/coreboot/+/52919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Gerrit-Change-Number: 52919 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 23:43:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
by Rob Barnes (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Marshall Dawson, Julian Schroeder, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52909 ) Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d Gerrit-Change-Number: 52909 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 23:35:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards
by Aseda Aboagye (Code Review) 04 May '21

04 May '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52920 ) Change subject: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards ...................................................................... mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards For dedede boards that use a discrete TPM, they will need to create the firmware management parameters TPM space. This commit simply selects that config option for those boards. BUG=b:184677625 BRANCH=None TEST=`emerge-keeby coreboot` Change-Id: I6c49f2018baa17df8c932b7a7d7f1aec28749ff2 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/mainboard/google/dedede/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/52920/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 3ec377e..6a7f3f3 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -164,4 +164,6 @@ hex default 0x24 # GPP_B4_IRQ +select TPM20_CREATE_FWMP + endif #BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c49f2018baa17df8c932b7a7d7f1aec28749ff2 Gerrit-Change-Number: 52920 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: chromeos/Kconfig: Add TPM20_CREATE_FWMP
by Aseda Aboagye (Code Review) 04 May '21

04 May '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52919 ) Change subject: chromeos/Kconfig: Add TPM20_CREATE_FWMP ...................................................................... chromeos/Kconfig: Add TPM20_CREATE_FWMP This commit adds a new config option, TPM20_CREATE_FWMP which instructs coreboot to create the Chrome OS Firmware Management Parameters space in the TPM. When selected, coreboot will simply define this space, but not initialize the contents. The space can be written to by the TPM owner from userspace. BUG=b:184677625 BRANCH=None TEST=emerge-keeby coreboot Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 --- M src/security/vboot/secdata_tpm.c M src/vendorcode/google/chromeos/Kconfig 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/52919/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index db5f2e7..7011039 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -10,6 +10,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <security/tpm/tss/tcg-1.2/tss_structures.h> +#include <security/tpm/tss/tcg-2.0/tss_structures.h> #include <vb2_api.h> #include <console/console.h> @@ -205,6 +206,8 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { + uint32_t rv; + vb2api_secdata_kernel_create(ctx); RETURN_ON_FAILURE(tlcl_force_clear()); @@ -227,6 +230,27 @@ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); + /* Define and write firmware management parameters space. */ + if (CONFIG(TPM20_CREATE_FWMP)) { + const TPMA_NV fwmp_attr = { + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_OWNERWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPREAD = 1, + }; + + VBDEBUG("TPM: Defining FMWP space\n") + rv = tlcl_define_space(FWMP_NV_INDEX, VB2_SECDATA_FWMP_MAX_SIZE, + fwmp_attr, pcr0_allowed_policy, + sizeof(pcr0_allowed_policy))); + if (rv == TPM_E_NV_DEFINED) { + VBDEBUG("TPM: FWMP space already defined\n"); + } else { + VBDEBUG("TPM: 0x%08x returned by tlcl_define_space\n", rv); + return rv; + } + } + RETURN_ON_FAILURE(set_firmware_space(ctx->secdata_firmware)); return TPM_SUCCESS; diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e6d45e1..b0ab2ec 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -92,5 +92,11 @@ bool depends on ACPI_SOC_NVS +config TPM20_CREATE_FWMP + def_bool n + depends on TPM2 + help + Instruct coreboot to create the firmware management parameters (FWMP) space in the TPM. + endif # CHROMEOS endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/52919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Gerrit-Change-Number: 52919 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Update AMDFW config file
by Marshall Dawson (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52900 ) Change subject: mb/google/mancomb: Update AMDFW config file ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg: https://review.coreboot.org/c/coreboot/+/52900/comment/93f0e62d_657d9331 PS1, Line 37: PSP_PMUI_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin : PSP_PMUD_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin It looks like you transposed the I and D in col. 8, comparing to soc//cezanne. So it looks like your Instr. file is Dmem and the Data file is Imem. -- To view, visit https://review.coreboot.org/c/coreboot/+/52900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Gerrit-Change-Number: 52900 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 04 May 2021 23:09:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT
by Raul Rangel (Code Review) 04 May '21

04 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT ...................................................................... soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT This will use the FSP PCI routing HOB to generate the PCI _PRT table. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/acpi_prt.c 3 files changed, 202 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52917/1 diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 081741a..a947ed6 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -5,6 +5,7 @@ #include <types.h> #include <soc/amd_pci_int_defs.h> +#include <device/device.h> /* FCH index/data registers */ #define PCI_INTR_INDEX 0xc00 @@ -33,5 +34,6 @@ /* Implemented by the SoC */ void populate_pirq_data(void); +void acpigen_write_pci_PRT(const struct device *dev, bool use_gnb_ioapic); #endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc index 9cfc9ff..42a460d 100644 --- a/src/soc/amd/common/fsp/pci/Makefile.inc +++ b/src/soc/amd/common/fsp/pci/Makefile.inc @@ -2,5 +2,6 @@ ramstage-y += pci_routing_info.c ramstage-y += pirq.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c endif # CONFIG_SOC_AMD_COMMON_FSP_PCI diff --git a/src/soc/amd/common/fsp/pci/acpi_prt.c b/src/soc/amd/common/fsp/pci/acpi_prt.c new file mode 100644 index 0000000..e408332 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/acpi_prt.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "pci_routing_info.h" +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <amdblocks/amd_pci_util.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <device/device.h> + +static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) +{ + unsigned int irq; + + acpigen_write_package(4); /* Package - APIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + /* GNB IO-APIC is located after the FCH IO-APIC */ + irq = IO_APIC_INTERRUPTS; + irq += pci_calculate_irq(routing_info, i); + + acpigen_write_PRT_source_entry( + 0, /* There is only one device attached to the bridge */ + i, /* pin */ + 0, /* Source: GSI */ + irq); + } + acpigen_pop_len(); /* Package - APIC Routing */ +} + +static void acpigen_write_PRT_PIC(const struct pci_routing_info *routing_info) +{ + unsigned int irq; + char link_template[] = "\\_SB.INTX"; + + acpigen_write_package(4); /* Package - PIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + irq = pci_calculate_irq(routing_info, i); + + link_template[8] = 'A' + (irq % 8); + + acpigen_write_PRT_source_entry( + 0, /* There is only one device attached to the bridge */ + i, /* pin */ + link_template, 0); + } + acpigen_pop_len(); /* Package - PIC Routing */ +} + +/* + * This method writes a PCI _PRT table: + * If use_gnb_ioapic is set we use the GNB IO-APIC / PIC: + * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + * { + * If (PICM) + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * 0x00, + * 0x00000034 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * 0x00, + * 0x00000035 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * 0x00, + * 0x00000036 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * 0x00, + * 0x00000037 + * } + * }) + * } + * Else + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.LNKA, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.LNKB, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.LNKC, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.LNKD, + * 0x00000000 + * } + * }) + * } + * } + * Otherwise we use the PIC / FCH IO-APIC: + * Name (_PRT, Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.LNKA, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.LNKB, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.LNKC, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.LNKD, + * 0x00000000 + * } + * }) + */ +void acpigen_write_pci_PRT(const struct device *dev, bool use_gnb_ioapic) +{ + const struct pci_routing_info *routing_info = + get_pci_routing_info(dev->path.pci.devfn); + + if (!routing_info) + return; + + if (use_gnb_ioapic) { + acpigen_write_method("_PRT", 0); + + /* If (PICM) */ + acpigen_write_if(); + acpigen_emit_namestring("PICM"); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_GSI(routing_info); + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_PIC(routing_info); + + acpigen_pop_len(); /* End Else */ + + acpigen_pop_len(); /* Method */ + } else { + acpigen_write_name("_PRT"); + acpigen_write_PRT_PIC(routing_info); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{common/picasso}: Move pci_int.asl
by Raul Rangel (Code Review) 04 May '21

04 May '21

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Change in coreboot[master]: mb/google/guybrush: Populate PIC IRQ data
by Raul Rangel (Code Review) 04 May '21

04 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52915 ) Change subject: mb/google/guybrush: Populate PIC IRQ data ...................................................................... mb/google/guybrush: Populate PIC IRQ data The PIC IRQs are required so we can correctly setup the PCI_INT registers. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f --- M src/mainboard/google/guybrush/mainboard.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52915/1 diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index b406bf3..1fe0af4 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -47,14 +47,14 @@ uint8_t pic_irq_num; uint8_t apic_irq_num; } guybrush_fch[] = { - { PIRQ_A, PIRQ_NC, PIRQ_NC }, - { PIRQ_B, PIRQ_NC, PIRQ_NC }, - { PIRQ_C, PIRQ_NC, PIRQ_NC }, - { PIRQ_D, PIRQ_NC, PIRQ_NC }, - { PIRQ_E, PIRQ_NC, PIRQ_NC }, - { PIRQ_F, PIRQ_NC, PIRQ_NC }, - { PIRQ_G, PIRQ_NC, PIRQ_NC }, - { PIRQ_H, PIRQ_NC, PIRQ_NC }, + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 13, PIRQ_NC }, + { PIRQ_C, 14, PIRQ_NC }, + { PIRQ_D, 15, PIRQ_NC }, + { PIRQ_E, 12, PIRQ_NC }, + { PIRQ_F, 13, PIRQ_NC }, + { PIRQ_G, 14, PIRQ_NC }, + { PIRQ_H, 15, PIRQ_NC }, { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, -- To view, visit https://review.coreboot.org/c/coreboot/+/52915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Gerrit-Change-Number: 52915 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021