Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Kane Chen, Karthik Ramasubramanian.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52874 )

Change subject: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
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Patch Set 5:

(2 comments)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/52874/comment/8cfd266c_5e5ec091 
PS5, Line 101: 	/*
             : 	 * Now that all APs have been relocated as well as the BSP let SMIs
             : 	 * start flowing.
             : 	 */
Can you please update all of these comments as to the reason why the `_no_powrbtn` variant is used here?

File src/soc/intel/alderlake/pmc.c:

https://review.coreboot.org/c/coreboot/+/52874/comment/400c5a5d_fce2dc5e 
PS5, Line 148: (FSPS) 
nit: space after `(`, also please spell it `FSP-S`