Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52895 )
Change subject: include/console: Fix duplicate entry of postcode 0x79 ......................................................................
include/console: Fix duplicate entry of postcode 0x79
Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x7c to avoid duplicate entry.
Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/arch/x86/c_start.S M src/include/console/post_codes.h 2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52895/1
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 19532d8..e515dbc 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -89,7 +89,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + post_code(POST_PRE_HARDWAREMAIN) /* post 7c */
andl $0xFFFFFFF0, %esp
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 69047f8..5af6734 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -175,13 +175,6 @@ #define POST_BS_WRITE_TABLES 0x79
/** - * \brief Pre call to RAM stage main() - * - * POSTed right before RAM stage main() is called from c_start.S - */ -#define POST_PRE_HARDWAREMAIN 0x79 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -196,6 +189,13 @@ #define POST_BS_PAYLOAD_BOOT 0x7b
/** + * \brief Pre call to RAM stage main() + * + * POSTed right before RAM stage main() is called from c_start.S + */ +#define POST_PRE_HARDWAREMAIN 0x7c + +/** * \brief Entry into coreboot in RAM stage main() * * This is the first call in hardwaremain.c. If this code is POSTed, then