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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52865
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ......................................................................
mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work due to the dependency on FSP-M PCIe configuration. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports.
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 --- M src/mainboard/intel/adlrvp/early_gpio_m.c 1 file changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52865/2