coreboot-gerrit May 2021

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Julius Werner, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51923 ) Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... Patch Set 6: (1 comment) File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/51923/comment/1e09f01d_1068b7fb PS6, Line 62: … [View More]

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Christian Walter (Code Review) 05 May '21

05 May '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Julius Werner, Arthur Heymans. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51923 ) Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail … [View More]

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Change in coreboot[master]: lib/coreboot_table.c: Remove unnecessary CPP use
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52729 ) Change subject: lib/coreboot_table.c: Remove unnecessary CPP use ...................................................................... lib/coreboot_table.c: Remove unnecessary CPP use Change-Id: Ib93617867b946e208c31275d55d380aab7e51a50 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52729 Tested-by: build bot (Jenkins) <no-reply(… [View More]

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Arthur Heymans, Morgan Jang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/52898/… [View More]

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Arthur Heymans, Morgan Jang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52898/comment/… [View More]

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Change in coreboot[master]: soc/intel/xeon_sp: Remove bogus SMRAM locking
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jonathan Zhang, Arthur Heymans, Patrick Rudolph. Hello Marc Jones, build bot (Jenkins), Jonathan Zhang, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51532 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Remove bogus SMRAM locking ...................................................................... soc/intel/xeon_sp: Remove bogus SMRAM locking From … [View More]

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Change in coreboot[master]: lib/coreboot_table.c: Remove unnecessary CPP use
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52729 ) Change subject: lib/coreboot_table.c: Remove unnecessary CPP use ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: … [View More]

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Change in coreboot[master]: security/tpm/crtm: Measure FMAP into TPM
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52753 ) Change subject: security/tpm/crtm: Measure FMAP into TPM ...................................................................... security/tpm/crtm: Measure FMAP into TPM FMAP is used to look up cbfs files or other FMAP regions so it should be measured too. TESTED: on qemu q35 with swtpm Change-Id: Ic424a094e7f790cce45c5a98b8bc6d46a8dcca1b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> … [View More]

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Change in coreboot[master]: mb/google/dedede: Add GPIO and SPD for pirika support
by Kirk Wang (Code Review) 05 May '21

05 May '21

Kirk Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52923 ) Change subject: mb/google/dedede: Add GPIO and SPD for pirika support ...................................................................... mb/google/dedede: Add GPIO and SPD for pirika support Add support for GPIO and SPD driver for pirika BUG=b:184157747 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Change-Id: … [View More]Id367a83b04aad62b7deabae99b3f91905a2fc46c --- A src/mainboard/google/dedede/variants/pirika/Makefile.inc A src/mainboard/google/dedede/variants/pirika/gpio.c M src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc M src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt 5 files changed, 61 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/52923/1 diff --git a/src/mainboard/google/dedede/variants/pirika/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/Makefile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/pirika/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c new file mode 100644 index 0000000..79646b5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP3300_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc index b0ca222..315f10f 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt index fa24790..d0b9209 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt index e4258b5..ae86d68 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt @@ -1,11 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. - -# Part Name +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/52923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Gerrit-Change-Number: 52923 Gerrit-PatchSet: 1 Gerrit-Owner: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation Do not use get_dram_base_mask to calculate system DRAM limits. Shift operation around values operating on base and mask were causing overflows and thus incorrect system DRAM limit. … [View More]Another function returning base and limit in KiB has been developed to avoid data loss. TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian with Linux 4.14 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 4 files changed, 137 insertions(+), 155 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/52922/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 020c9c6..4aed96b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,29 +26,6 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned int fx_devs = 0; -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - struct dram_base_mask_t d; - dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] - d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too - - temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] - d.mask |= (temp & 1); // read enable bit - - d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too - - return d; -} - static u32 get_io_addr_index(u32 nodeid, u32 linkn) { return 0; @@ -127,6 +104,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[35:24], 00_0000h} <= address[35:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0x0fff0000)) >> (10 - 8); + /* + * BKDG address[35:0] <= {DramLimit[35:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0x0fff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -305,10 +309,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - struct dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(0); - if (d.mask & 1) { + + if (get_dram_base_limit(0, &basek, &limitk)) { hole = pci_read_config32(__f1_dev[0], 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -542,27 +546,13 @@ #endif idx = 0x10; - - struct dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(0); + if (get_dram_base_limit(0, &basek, &limitk)) { + sizek = limitk - basek; - if (d.mask & 1) { - basek = ((resource_t) ((u64) d.base)) << 8; - limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF); - printk(BIOS_DEBUG, - "adsr: (before) basek = %llx, limitk = %llx.\n", basek, - limitk); - - /* Convert these values to multiples of 1K for ease of math. */ - basek >>= 10; - limitk >>= 10; - sizek = limitk - basek + 1; - - printk(BIOS_DEBUG, - "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n", - basek, limitk, sizek); + printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", + basek, limitk, sizek); /* see if we need a hole from 0xa0000 to 0xbffff */ if ((basek < 640) && (sizek > 768)) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index e345b50..580153c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -24,11 +24,6 @@ #define MAX_NODE_NUMS MAX_NODES -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -37,24 +32,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -125,6 +102,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam15_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -616,10 +620,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -634,18 +638,16 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + u32 hole; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -698,14 +700,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b600bc9..21b4d69 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -24,11 +24,6 @@ #define MAX_NODE_NUMS MAX_NODES -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -37,24 +32,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -125,6 +102,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -634,10 +638,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -652,18 +656,15 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -716,14 +717,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 2019fae..e1ff95a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,11 +29,6 @@ #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -42,24 +37,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -130,6 +107,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -970,10 +974,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; @@ -988,18 +992,15 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -1050,14 +1051,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange [View Less]

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coreboot-gerrit May 2021