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Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/52898/comment/5984c2e4_4beaabbf
PS1, Line 211: current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base);
Hmmm... Maybe the issue is that the else-branch got moved.
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Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52898/comment/6e79b44b_cb4fa69f
PS1, Line 10: This broke DMAR. DRHD defines the scope of the device entries below.
Could you please add the error messages that the broken DMAR caused?
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Hello Marc Jones, build bot (Jenkins), Jonathan Zhang, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51532
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Remove bogus SMRAM locking
......................................................................
soc/intel/xeon_sp: Remove bogus SMRAM locking
From tests this does not lock down SMRAM and it's also not possible to
read back what is written, be it via PCI mmconfig or io ops. The
FSP integration can be assumed to be bogus on this point.
Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/cpx/chip.c
1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/51532/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52729 )
Change subject: lib/coreboot_table.c: Remove unnecessary CPP use
......................................................................
Patch Set 1: Code-Review+2
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Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52753 )
Change subject: security/tpm/crtm: Measure FMAP into TPM
......................................................................
security/tpm/crtm: Measure FMAP into TPM
FMAP is used to look up cbfs files or other FMAP regions so it should
be measured too.
TESTED: on qemu q35 with swtpm
Change-Id: Ic424a094e7f790cce45c5a98b8bc6d46a8dcca1b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52753
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/security/tpm/tspi/crtm.c
1 file changed, 11 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c
index 80483d5..0841d23 100644
--- a/src/security/tpm/tspi/crtm.c
+++ b/src/security/tpm/tspi/crtm.c
@@ -59,6 +59,17 @@
return VB2_SUCCESS;
}
+ struct region_device fmap;
+ if (fmap_locate_area_as_rdev("FMAP", &fmap) == 0) {
+ if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "FMAP: FMAP")) {
+ printk(BIOS_ERR,
+ "TSPI: Couldn't measure FMAP into CRTM!\n");
+ return VB2_ERROR_UNKNOWN;
+ }
+ } else {
+ printk(BIOS_ERR, "TSPI: Could not find FMAP!\n");
+ }
+
/* measure bootblock from RO */
struct cbfsf bootblock_data;
struct region_device bootblock_fmap;
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Kirk Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52923 )
Change subject: mb/google/dedede: Add GPIO and SPD for pirika support
......................................................................
mb/google/dedede: Add GPIO and SPD for pirika support
Add support for GPIO and SPD driver for pirika
BUG=b:184157747
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com>
Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c
---
A src/mainboard/google/dedede/variants/pirika/Makefile.inc
A src/mainboard/google/dedede/variants/pirika/gpio.c
M src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc
M src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
5 files changed, 61 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/52923/1
diff --git a/src/mainboard/google/dedede/variants/pirika/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/Makefile.inc
new file mode 100644
index 0000000..eb2c9bc
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/pirika/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c
new file mode 100644
index 0000000..79646b5
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/pirika/gpio.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+
+ /* A11 : TOUCH_RPT_EN */
+ PAD_NC(GPP_A11, NONE),
+
+ /* C18 : AP_I2C_EMR_SDA */
+ PAD_NC(GPP_C18, NONE),
+ /* C19 : AP_I2C_EMR_SCL */
+ PAD_NC(GPP_C19, NONE),
+
+ /* D12 : WCAM_RST_L */
+ PAD_NC(GPP_D12, NONE),
+ /* D13 : EN_PP3300_CAMERA */
+ PAD_CFG_GPO(GPP_D13, 1, PLTRST),
+ /* D14 : EN_PP1200_CAMERA */
+ PAD_NC(GPP_D14, NONE),
+ /* D15 : UCAM_RST_L */
+ PAD_NC(GPP_D15, NONE),
+ /* D19 : WWAN_WLAN_COEX1 */
+ PAD_NC(GPP_D19, NONE),
+ /* D20 : WWAN_WLAN_COEX2 */
+ PAD_NC(GPP_D20, NONE),
+ /* D21 : WWAN_WLAN_COEX3 */
+ PAD_NC(GPP_D21, NONE),
+
+ /* E2 : CLK_24M_WCAM */
+ PAD_NC(GPP_E2, NONE),
+ /* E17 : HDMI_DDC_SCL */
+ PAD_NC(GPP_E17, NONE),
+
+ /* H6 : AP_I2C_CAM_SDA */
+ PAD_NC(GPP_H6, NONE),
+ /* H7 : AP_I2C_CAM_SCL */
+ PAD_NC(GPP_H7, NONE),
+
+ /* S2 : DMIC1_CLK */
+ PAD_NC(GPP_S2, NONE),
+ /* S3 : DMIC1_DATA */
+ PAD_NC(GPP_S3, NONE),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc
index b0ca222..315f10f 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc
@@ -1,5 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
index fa24790..d0b9209 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
@@ -1 +1,3 @@
DRAM Part Name ID to assign
+H9HCNNNBKMMLXR-NEE 0 (0000)
+K4U6E3S4AA-MGCR 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
index e4258b5..ae86d68 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
@@ -1,11 +1,2 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
+H9HCNNNBKMMLXR-NEE
+K4U6E3S4AA-MGCR
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 )
Change subject: include/console: Fix duplicate entry of postcode 0x79
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52895/comment/ed25590e_e2434f41
PS3, Line 13: to make the ramstage postcodes appear in an incremental order.
> This should be done in another commit.
make sense, will wait for Nico to share his thought on this and then i will split this CL?
File src/include/console/post_codes.h:
https://review.coreboot.org/c/coreboot/+/52895/comment/c52170ce_d4cf87fb
PS3, Line 190: POST_BS_WRITE_TABLES
> grep says this macro is unused. […]
make sense
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Change subject: include/console: Fix duplicate entry of postcode 0x79
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52895/comment/97bc07fe_3a6b868a
PS3, Line 13: to make the ramstage postcodes appear in an incremental order.
This should be done in another commit.
File src/include/console/post_codes.h:
https://review.coreboot.org/c/coreboot/+/52895/comment/6efea113_5e1e2d1c
PS3, Line 190: POST_BS_WRITE_TABLES
grep says this macro is unused. I'd rather renumber (or remove) this instead of POST_PRE_HARDWAREMAIN.
File src/include/console/post_codes.h:
https://review.coreboot.org/c/coreboot/+/52895/comment/f96c04eb_98fc5f45
PS1, Line 191: /**
: * \brief Pre call to RAM stage main()
: *
: * POSTed right before RAM stage main() is called from c_start.S
: */
: #define POST_PRE_HARDWAREMAIN 0x7c
:
: /**
: * \brief Entry into coreboot in RAM stage main()
: *
: * This is the first call in hardwaremain.c. If this code is POSTed, then
: * ramstage has successfully loaded and started executing.
: */
: #define POST_ENTRY_RAMSTAGE 0x80
> Perfect, done
I'd say it doesn't matter.
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