coreboot-gerrit May 2021

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Change in coreboot[master]: soc/mediatek/mt8195: Add SPI driver support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52669 ) Change subject: soc/mediatek/mt8195: Add SPI driver support ...................................................................... soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/pll.h M src/soc/mediatek/mt8195/include/soc/spi.h M src/soc/mediatek/mt8195/spi.c 4 files changed, 114 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 1f2d1de..04f4572 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -4,13 +4,13 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c verstage-y += ../common/gpio.c gpio.c -verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c @@ -19,7 +19,7 @@ romstage-y += emi.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/pll.c pll.c -romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c @@ -31,7 +31,7 @@ ramstage-y += emi.c ramstage-y += ../common/gpio.c gpio.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h index 6d836f7..60fcbd9 100644 --- a/src/soc/mediatek/mt8195/include/soc/pll.h +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -562,10 +562,12 @@ /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2, }; /* top_mux rate */ enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, UART_HZ = CLK26M_HZ, }; diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h index cfa4f43..a74ed56 100644 --- a/src/soc/mediatek/mt8195/include/soc/spi.h +++ b/src/soc/mediatek/mt8195/include/soc/spi.h @@ -3,6 +3,21 @@ #ifndef MTK_MT8195_SPI_H #define MTK_MT8195_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index 459e46a..bc02aa0 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -1,15 +1,107 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/gpio.h> #include <soc/spi.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPIM0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPIM1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPIM2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(PWRAP_SPI_CSN), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(DGI_D2), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(DGI_D6), + }, +}; + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPIM0_MI, SPIM0_MI), + PAD_FUNC_GPIO(SPIM0_CSB), + PAD_FUNC(SPIM0_MO, SPIM0_MO), + PAD_FUNC(SPIM0_CLK, SPIM0_CLK), + }, + { + PAD_FUNC(SPIM1_MI, SPIM1_MI), + PAD_FUNC_GPIO(SPIM1_CSB), + PAD_FUNC(SPIM1_MO, SPIM1_MO), + PAD_FUNC(SPIM1_CLK, SPIM1_CLK), + }, + { + PAD_FUNC(SPIM2_MI, PIM2_MI), + PAD_FUNC_GPIO(SPIM2_CSB), + PAD_FUNC(SPIM2_MO, SPIM2_MO), + PAD_FUNC(SPIM2_CLK, SPIM2_CLK), + }, + { + PAD_FUNC(PWRAP_SPI_MI, SPIM3_MI), + PAD_FUNC_GPIO(PWRAP_SPI_CSN), + PAD_FUNC(PWRAP_SPI_MO, SPIM3_MO), + PAD_FUNC(PWRAP_SPI_CK, SPIM3_CLK), + }, + { + PAD_FUNC(DGI_D3, SPIM4_MI), + PAD_FUNC_GPIO(DGI_D2), + PAD_FUNC(DGI_D1, SPIM4_MO), + PAD_FUNC(DGI_D0, SPIM4_CLK), + }, + { + PAD_FUNC(DGI_D7, SPIM5_MI), + PAD_FUNC_GPIO(DGI_D6), + PAD_FUNC(DGI_D5, SPIM5_MO), + PAD_FUNC(DGI_D4, SPIM5_CLK), + }, +}; + +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + assert(pad_select == SPI_PAD0_MASK); + const struct pad_func *ptr = NULL; + + ptr = pad0_funcs[bus]; + for (int i = 0; i < 4; i++) + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Gerrit-Change-Number: 52669 Gerrit-PatchSet: 17 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Move the common part of SPI drivers to common/
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52854 ) Change subject: soc/mediatek: Move the common part of SPI drivers to common/ ...................................................................... soc/mediatek: Move the common part of SPI drivers to common/ The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c M src/soc/mediatek/mt8192/include/soc/spi.h M src/soc/mediatek/mt8192/spi.c 8 files changed, 61 insertions(+), 148 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 918f3d2..a70b9b1 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -3,21 +3,12 @@ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H +#include <device/mmio.h> #include <soc/gpio_base.h> #include <spi-generic.h> #include <types.h> enum { - SPI_CFG1_CS_IDLE_SHIFT = 0, - SPI_CFG1_PACKET_LOOP_SHIFT = 8, - SPI_CFG1_PACKET_LENGTH_SHIFT = 16, - - SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, - SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, - SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, -}; - -enum { SPI_CMD_ACT_SHIFT = 0, SPI_CMD_RESUME_SHIFT = 1, SPI_CMD_RST_SHIFT = 2, @@ -59,7 +50,24 @@ SPI_PAD_SEL_MASK = 0x3 }; -struct mtk_spi_regs; +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); struct mtk_spi_bus { struct spi_slave slave; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index afc64c6..f465027 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -34,6 +34,19 @@ return &spi_bus[slave->bus]; } +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, + u32 cs_ticks, unsigned int tick_dly) +{ + SET32_BITFIELDS(&regs->spi_cfg0_reg, SPI_CFG_CS_HOLD, cs_ticks - 1, + SPI_CFG_CS_SETUP, cs_ticks - 1); + + SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1, + SPI_CFG_SCK_HIGH, sck_ticks - 1); + + SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly, + SPI_CFG1_CS_IDLE, cs_ticks - 1); +} + static void spi_sw_reset(struct mtk_spi_regs *regs) { setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); @@ -121,10 +134,8 @@ else size = MIN(*bytes_in, *bytes_out); - clrsetbits32(&regs->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_PACKET_LENGTH, size - 1, + SPI_CFG1_PACKET_LOOP, 0); if (*bytes_out) { const uint8_t *outb = (const uint8_t *)out; diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 47da0f8..b267aa0 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -7,32 +7,16 @@ #define SPI_BUS_NUMBER 1 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg0_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8) +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 23, 16) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24) -enum { - SPI_CFG0_SCK_HIGH_SHIFT = 0, - SPI_CFG0_SCK_LOW_SHIFT = 8, - SPI_CFG0_CS_HOLD_SHIFT = 16, - SPI_CFG0_CS_SETUP_SHIFT = 24, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 30, - SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 4abd650..d3c8ad4 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -26,20 +26,6 @@ gpio_set_mode(GPIO(MSDC2_CMD), 0); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | - SPI_CFG1_TICK_DLY_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 5efa618..5bc70e5 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -7,39 +7,18 @@ #define SPI_BUS_NUMBER 6 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg2_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, - -}; #endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 87362dc..c172f37 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -103,23 +103,6 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(&regs->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h index 034fa35..db3ba21 100644 --- a/src/soc/mediatek/mt8192/include/soc/spi.h +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -7,38 +7,17 @@ #define SPI_BUS_NUMBER 8 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; +#define GET_SCK_REG(x) x->spi_cfg2_reg -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, -}; +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index f7a8756..b5abc85 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -112,23 +112,6 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(&regs->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(&regs->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, -- To view, visit https://review.coreboot.org/c/coreboot/+/52854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Gerrit-Change-Number: 52854 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Shaunak Saha, Martin Roth, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51649 ) Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads ...................................................................... Patch Set 23: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/51649/comment/7d679dad_314c8880 PS22, Line 333: MAX_TYPE_C_PORTS > Haha, you know much more than me ;). […] If this ever needs to be changed, I'd prefer a Kconfig option. If a Kconfig option is not meant to be user-configurable, just don't give it a prompt. -- To view, visit https://review.coreboot.org/c/coreboot/+/51649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Gerrit-Change-Number: 51649 Gerrit-PatchSet: 23 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 07:36:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Initialize pmif/spmi/pmic in romstage
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52849 ) Change subject: mb/google/cherry: Initialize pmif/spmi/pmic in romstage ...................................................................... mb/google/cherry: Initialize pmif/spmi/pmic in romstage Signed-off-by: Henry Chen <henryc.chen(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52849 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/romstage.c 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index ada29aa..4831a39 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -7,6 +7,7 @@ romstage-y += memlayout.ld romstage-y += chromeos.c +romstage-y += romstage.c ramstage-y += memlayout.ld ramstage-y += chromeos.c diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c new file mode 100644 index 0000000..cba5995 --- /dev/null +++ b/src/mainboard/google/cherry/romstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/mt6315.h> +#include <soc/mt6359p.h> +#include <soc/pmif.h> + +void platform_romstage_main(void) +{ + mtk_pmif_init(); + mt6359p_init(); + mt6315_init(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a Gerrit-Change-Number: 52849 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52668 ) Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... soc/mediatek/mt8195: add pmif/spmi/pmic driver MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/include/soc/pmif_clk_common.h M src/soc/mediatek/common/include/soc/pmif_spmi.h M src/soc/mediatek/common/include/soc/pmif_sw.h A src/soc/mediatek/common/pmif_clk.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/pmif_clk.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/iocfg.h A src/soc/mediatek/mt8195/include/soc/pmif.h A src/soc/mediatek/mt8195/mt6315.c A src/soc/mediatek/mt8195/mt6359p.c A src/soc/mediatek/mt8195/pmif_clk.c A src/soc/mediatek/mt8195/pmif_spi.c A src/soc/mediatek/mt8195/pmif_spmi.c 15 files changed, 946 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/pmif_clk_common.h b/src/soc/mediatek/common/include/soc/pmif_clk_common.h new file mode 100644 index 0000000..f1bd2c7 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pmif_clk_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MEDIATEK_SOC_PMIF_CLK_COMMON__ +#define __MEDIATEK_SOC_PMIF_CLK_COMMON__ + +int pmif_ulposc_cali(u32 target_val); + +#endif /*__MEDIATEK_SOC_PMIF_CLK_COMMON__*/ diff --git a/src/soc/mediatek/common/include/soc/pmif_spmi.h b/src/soc/mediatek/common/include/soc/pmif_spmi.h index 142217d..b6088b8 100644 --- a/src/soc/mediatek/common/include/soc/pmif_spmi.h +++ b/src/soc/mediatek/common/include/soc/pmif_spmi.h @@ -25,7 +25,8 @@ u32 op_st_sta; u32 mst_sampl; u32 mst_req_en; - u32 reserved1[11]; + u32 rcs_ctrl; + u32 reserved1[10]; u32 rec_ctrl; u32 rec0; u32 rec1; diff --git a/src/soc/mediatek/common/include/soc/pmif_sw.h b/src/soc/mediatek/common/include/soc/pmif_sw.h index 3b3e4df..ea26446 100644 --- a/src/soc/mediatek/common/include/soc/pmif_sw.h +++ b/src/soc/mediatek/common/include/soc/pmif_sw.h @@ -23,5 +23,6 @@ CAL_MAX_VAL = 0x7F, }; +u32 pmif_get_ulposc_freq_mhz(u32 cali_val); int pmif_clk_init(void); #endif /* __SOC_MEDIATEK_PMIF_SW_H__ */ diff --git a/src/soc/mediatek/common/pmif_clk.c b/src/soc/mediatek/common/pmif_clk.c new file mode 100644 index 0000000..5b458a0 --- /dev/null +++ b/src/soc/mediatek/common/pmif_clk.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <soc/pmif_clk_common.h> +#include <soc/pmif_sw.h> + +int pmif_ulposc_cali(u32 target_val) +{ + u32 current_val, min = 0, max = CAL_MAX_VAL, middle; + int diff_by_min, diff_by_max, cal_result; + + do { + middle = (min + max) / 2; + if (middle == min) + break; + + current_val = pmif_get_ulposc_freq_mhz(middle); + if (current_val > target_val) + max = middle; + else + min = middle; + } while (min <= max); + + diff_by_min = pmif_get_ulposc_freq_mhz(min) - target_val; + diff_by_min = ABS(diff_by_min); + + diff_by_max = pmif_get_ulposc_freq_mhz(max) - target_val; + diff_by_max = ABS(diff_by_max); + + cal_result = (diff_by_min < diff_by_max) ? min : max; + current_val = pmif_get_ulposc_freq_mhz(cal_result); + + /* check if calibrated value is in the range of target value +- 15% */ + if (current_val < (target_val * (1000 - CAL_TOL_RATE) / 1000) || + current_val > (target_val * (1000 + CAL_TOL_RATE) / 1000)) { + printk(BIOS_ERR, "[%s] calibration fail: cur=%d, CAL_RATE=%d, target=%dM\n", + __func__, current_val, CAL_TOL_RATE, target_val); + return 1; + } + + return 0; +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 865ff40..e2abc5e 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -35,7 +35,7 @@ romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c -romstage-y += ../common/pmif.c pmif_clk.c +romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c romstage-y += ../common/pmif_spmi.c pmif_spmi.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c index a597b6a..e5c0d1d 100644 --- a/src/soc/mediatek/mt8192/pmif_clk.c +++ b/src/soc/mediatek/mt8192/pmif_clk.c @@ -8,6 +8,7 @@ #include <soc/pll.h> #include <soc/pll_common.h> #include <soc/pmif.h> +#include <soc/pmif_clk_common.h> #include <soc/pmif_sw.h> #include <soc/pmif_spmi.h> #include <soc/spm.h> @@ -72,7 +73,7 @@ SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x40); } -static u32 pmif_get_ulposc_freq_mhz(u32 cali_val) +u32 pmif_get_ulposc_freq_mhz(u32 cali_val) { u32 result = 0; @@ -84,47 +85,6 @@ return result / 1000; } -static int pmif_ulposc_cali(u32 target_val) -{ - u32 current_val = 0, min = 0, max = CAL_MAX_VAL, middle; - int ret = 0, diff_by_min, diff_by_max, cal_result; - - do { - middle = (min + max) / 2; - if (middle == min) - break; - - current_val = pmif_get_ulposc_freq_mhz(middle); - if (current_val > target_val) - max = middle; - else - min = middle; - } while (min <= max); - - diff_by_min = pmif_get_ulposc_freq_mhz(min) - target_val; - diff_by_min = ABS(diff_by_min); - - diff_by_max = pmif_get_ulposc_freq_mhz(max) - target_val; - diff_by_max = ABS(diff_by_max); - - if (diff_by_min < diff_by_max) { - cal_result = min; - current_val = pmif_get_ulposc_freq_mhz(min); - } else { - cal_result = max; - current_val = pmif_get_ulposc_freq_mhz(max); - } - - /* check if calibrated value is in the range of target value +- 15% */ - if (current_val < (target_val * (1000 - CAL_TOL_RATE) / 1000) || - current_val > (target_val * (1000 + CAL_TOL_RATE) / 1000)) { - printk(BIOS_ERR, "[%s] calibration fail: %dM\n", __func__, current_val); - ret = 1; - } - - return ret; -} - static int pmif_init_ulposc(void) { /* calibrate ULPOSC1 */ diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index b3e12e9..1f2d1de 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -23,6 +23,11 @@ romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c +romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c +romstage-y += ../common/pmif_spi.c pmif_spi.c +romstage-y += ../common/pmif_spmi.c pmif_spmi.c +romstage-y += ../common/mt6315.c mt6315.c +romstage-y += ../common/mt6359p.c mt6359p.c ramstage-y += emi.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index 85d0fad..db24b77 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -41,6 +41,7 @@ DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, + SCP_CFG_BASE = IO_PHYS + 0x00700000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, diff --git a/src/soc/mediatek/mt8195/include/soc/iocfg.h b/src/soc/mediatek/mt8195/include/soc/iocfg.h new file mode 100644 index 0000000..8ca2f62 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/iocfg.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_IOCFG_H__ +#define __SOC_MEDIATEK_MT8195_IOCFG_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8195_iocfg_bm_regs { + u32 reserved1[4]; + u32 drv_cfg1; + u32 drv_cfg1_set; + u32 drv_cfg1_clr; + u32 reserved2; + u32 drv_cfg2; + u32 drv_cfg2_set; + u32 drv_cfg2_clr; + u32 reserved3; + u32 drv_cfg3; + u32 drv_cfg3_set; + u32 drv_cfg3_clr; + u32 reserved4[1]; + u32 eh_cfg; + u32 eh_cfg_set; + u32 eh_cfg_clr; + u32 reserved5[9]; + u32 ies_cfg1; + u32 ies_cfg1_set; + u32 ies_cfg1_clr; + u32 reserved6[5]; + u32 pd_cfg1; + u32 pd_cfg1_set; + u32 pd_cfg1_clr; + u32 reserved7[5]; + u32 pu_cfg1; + u32 pu_cfg1_set; + u32 pu_cfg1_clr; + u32 reserved8[1]; + u32 rdsel_cfg0; + u32 rdsel_cfg0_set; + u32 rdsel_cfg0_clr; + u32 reserved9[9]; + u32 smt_cfg0; + u32 smt_cfg0_set; + u32 smt_cfg0_clr; + u32 reserved10[5]; + u32 tdsel_cfg1; + u32 tdsel_cfg1_set; + u32 tdsel_cfg1_clr; +}; +check_member(mt8195_iocfg_bm_regs, drv_cfg1, 0x10); +check_member(mt8195_iocfg_bm_regs, drv_cfg2, 0x20); +check_member(mt8195_iocfg_bm_regs, drv_cfg3, 0x30); +check_member(mt8195_iocfg_bm_regs, eh_cfg, 0x40); +check_member(mt8195_iocfg_bm_regs, ies_cfg1, 0x70); +check_member(mt8195_iocfg_bm_regs, pd_cfg1, 0x90); +check_member(mt8195_iocfg_bm_regs, pu_cfg1, 0xB0); +check_member(mt8195_iocfg_bm_regs, rdsel_cfg0, 0xC0); +check_member(mt8195_iocfg_bm_regs, smt_cfg0, 0xF0); +check_member(mt8195_iocfg_bm_regs, tdsel_cfg1, 0x110); + +#define mtk_iocfg_bm ((struct mt8195_iocfg_bm_regs *)IOCFG_BM_BASE) + +enum { + IO_4_MA = 0x9, +}; +#endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h new file mode 100644 index 0000000..992549f --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pmif.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT8195_SOC_PMIF_H__ +#define __MT8195_SOC_PMIF_H__ + +#include <device/mmio.h> +#include <soc/pmif_common.h> +#include <types.h> + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_ctrl; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[6]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[244]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0); +check_member(mtk_pmif_regs, crc_ctrl, 0x39C); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B8); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E4); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414); +check_member(mtk_pmif_regs, irq_event_en_0, 0x420); +check_member(mtk_pmif_regs, swinf_0_acc, 0x800); + +#define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0x880) +#define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0x880) + +struct mtk_scp_regs { + u32 reserved[27]; + u32 scp_clk_on_ctrl; +}; + +check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C); + +#define mtk_scp ((struct mtk_scp_regs *)SCP_CFG_BASE + 0x21000) + +enum { + FREQ_248MHZ = 248, +}; + +#define FREQ_METER_ABIST_AD_OSC_CK 48 +#endif /*__MT8195_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8195/mt6315.c b/src/soc/mediatek/mt8195/mt6315.c new file mode 100644 index 0000000..3a0fad1 --- /dev/null +++ b/src/soc/mediatek/mt8195/mt6315.c @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/mt6315.h> + +static const struct mt6315_setting init_setting_cpu[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* clear boot status */ + {0x12A, 0x3, 0xFF, 0}, + {0xD, 1, 0x1, 0}, + {0xD, 0, 0x1, 0}, + {0x1416, 0xF, 0xF, 0}, + /* init setting */ + {0x997, 0xF, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xE, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x3, 0x7F, 0}, + {0x148C, 0x3, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x3, 0x7F, 0}, + {0x150C, 0x3, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x3, 0x7F, 0}, + {0x158C, 0x3, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x3, 0x7F, 0}, + {0x160C, 0x3, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xF, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0xC, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x3, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xF, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0xC, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x3, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xF, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0xFF, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0xC, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x3, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xF, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0xC, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x3, 0x3F, 0}, + {0x16CE, 0x0, 0x8, 0}, + + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static const struct mt6315_setting init_setting_gpu[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3a2, 0x2A, 0xFF, 0}, + {0x3a1, 0x7C, 0xFF, 0}, + /* init setting */ + {0x997, 0x7, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0x1F, 0x1F, 0}, + {0x9A3, 0x1F, 0x1F, 0}, + {0x1440, 0xC, 0xE, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x4, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x4, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x78, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x4, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x20, 0x76, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0x80, 0xE1, 0}, + {0x169E, 0xFC, 0xFF, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xDB, 0xFF, 0}, + {0x16A3, 0xA1, 0xFF, 0}, + {0x16A4, 0x1, 0x3F, 0}, + {0x16A5, 0x20, 0x76, 0}, + {0x16A6, 0xD, 0x2F, 0}, + {0x16A7, 0x81, 0xE1, 0}, + {0x16A8, 0xFC, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xDB, 0xFF, 0}, + {0x16AD, 0xA1, 0xFF, 0}, + {0x16AE, 0x3, 0x3F, 0}, + {0x16CE, 0x8, 0x8, 0}, + + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +void mt6315_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++) + mt6315_write_field(MT6315_CPU, + init_setting_cpu[i].addr, init_setting_cpu[i].val, + init_setting_cpu[i].mask, init_setting_cpu[i].shift); + + for (int i = 0; i < ARRAY_SIZE(init_setting_gpu); i++) + mt6315_write_field(MT6315_GPU, + init_setting_gpu[i].addr, init_setting_gpu[i].val, + init_setting_gpu[i].mask, init_setting_gpu[i].shift); +} diff --git a/src/soc/mediatek/mt8195/mt6359p.c b/src/soc/mediatek/mt8195/mt6359p.c new file mode 100644 index 0000000..fbb5005 --- /dev/null +++ b/src/soc/mediatek/mt8195/mt6359p.c @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/mt6359p.h> + +static const struct pmic_setting init_setting[] = { + {0x20, 0xA, 0xA, 0}, + {0x24, 0x1F00, 0x1F00, 0}, + {0x30, 0x1, 0x1, 0}, + {0x32, 0x1, 0x1, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x10, 0x10, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x14A, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x1B2, 0x3, 0x3, 0}, + {0x3B0, 0x0, 0x300, 0}, + {0x790, 0x3, 0x3, 0}, + {0x796, 0x1750, 0x3FFF, 0}, + {0x798, 0x1750, 0x3FFF, 0}, + {0x7A6, 0xF800, 0xFC00, 0}, + {0x7A8, 0x80, 0x280, 0}, + {0x98A, 0x80, 0x80, 0}, + {0x992, 0xF00, 0xF00, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA0C, 0x300, 0x300, 0}, + {0xA10, 0x0, 0x4000, 0}, + {0xA12, 0x1E0, 0x1E0, 0}, + {0xA24, 0xFFFF, 0xFFFF, 0}, + {0xA26, 0xFFE0, 0xFFE0, 0}, + {0xA2C, 0xC0DF, 0xC0DF, 0}, + {0xA2E, 0xEBE0, 0xEBE0, 0}, + {0xA34, 0x8000, 0x8000, 0}, + {0xA3C, 0x1500, 0x1F00, 0}, + {0xA3E, 0x4261, 0x7FFF, 0}, + {0xA40, 0x3842, 0x7FFF, 0}, + {0xA42, 0xC03, 0x7FFF, 0}, + {0xA44, 0x1CC4, 0x7FFF, 0}, + {0xA46, 0x21AD, 0x7FFF, 0}, + {0xA48, 0x5409, 0x7FFF, 0}, + {0xA4A, 0x46AA, 0x7FFF, 0}, + {0xA4C, 0x3E90, 0x7FFF, 0}, + {0xA4E, 0x5253, 0x7FFF, 0}, + {0xA50, 0xA0, 0x7FFF, 0}, + {0xA9C, 0x4000, 0x4000, 0}, + {0xA9E, 0x2E11, 0xFF11, 0}, + {0xF8C, 0x115, 0x115, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x1198, 0x13, 0x3FF, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11D4, 0x0, 0x2, 0}, + {0x1212, 0x0, 0x2, 0}, + {0x1224, 0x0, 0x2, 0}, + {0x1238, 0x0, 0x2, 0}, + {0x124A, 0x0, 0x2, 0}, + {0x125C, 0x0, 0x2, 0}, + {0x125E, 0x0, 0x8000, 0}, + {0x1260, 0x1, 0xFFF, 0}, + {0x1262, 0x4, 0x4, 0}, + {0x1412, 0x8, 0x8, 0}, + {0x148E, 0x18, 0x7F, 0}, + {0x1492, 0xF1F, 0x7F7F, 0}, + {0x150E, 0x18, 0x7F, 0}, + {0x1512, 0xF15, 0x7F7F, 0}, + {0x158E, 0x18, 0x7F, 0}, + {0x1592, 0xF00, 0x7F00, 0}, + {0x160E, 0x18, 0x7F, 0}, + {0x1692, 0xF1F, 0x7F7F, 0}, + {0x170E, 0x18, 0x7F, 0}, + {0x1712, 0xF1F, 0x7F7F, 0}, + {0x178E, 0x18, 0x7F, 0}, + {0x1792, 0xF1F, 0x7F7F, 0}, + {0x1918, 0x0, 0x3F3F, 0}, + {0x191A, 0x0, 0x3F00, 0}, + {0x198A, 0x5004, 0x502C, 0}, + {0x198C, 0x3E, 0x3F, 0}, + {0x198E, 0x1E0, 0x1E0, 0}, + {0x1990, 0xFD, 0xFF, 0}, + {0x1994, 0x10, 0x38, 0}, + {0x1996, 0x2004, 0xA02C, 0}, + {0x1998, 0x3E, 0x3F, 0}, + {0x199A, 0xFB78, 0xFF78, 0}, + {0x199E, 0x2, 0x7, 0}, + {0x19A0, 0x1050, 0x10F1, 0}, + {0x19A2, 0x3E, 0x3F, 0}, + {0x19A4, 0xFD0F, 0xFF0F, 0}, + {0x19A6, 0x20, 0xFF, 0}, + {0x19AC, 0x4208, 0x4698, 0}, + {0x19AE, 0x6E, 0x7E, 0}, + {0x19B0, 0x3C00, 0x3C00, 0}, + {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x1A08, 0x4208, 0x4698, 0}, + {0x1A0A, 0x6E, 0x7E, 0}, + {0x1A0C, 0x3C00, 0x3C00, 0}, + {0x1A10, 0x20FD, 0xFFFF, 0}, + {0x1A14, 0x4208, 0x4698, 0}, + {0x1A16, 0x6E, 0x7E, 0}, + {0x1A18, 0x3C00, 0x3C00, 0}, + {0x1A1C, 0x20FD, 0xFFFF, 0}, + {0x1A1E, 0x0, 0x200, 0}, + {0x1A20, 0x4208, 0x4698, 0}, + {0x1A22, 0x4A, 0x7E, 0}, + {0x1A24, 0x3C00, 0x3C00, 0}, + {0x1A28, 0x3000, 0xFF00, 0}, + {0x1A2C, 0x20, 0x74, 0}, + {0x1A2E, 0x1E, 0x1E, 0}, + {0x1A30, 0x42, 0xFF, 0}, + {0x1A32, 0x480, 0x7E0, 0}, + {0x1A34, 0x20, 0x74, 0}, + {0x1A36, 0x1E, 0x1E, 0}, + {0x1A38, 0x42, 0xFF, 0}, + {0x1A3A, 0x480, 0x7E0, 0}, + {0x1A3C, 0x14C, 0x3CC, 0}, + {0x1A3E, 0x23C, 0x3FC, 0}, + {0x1A40, 0xC400, 0xFF00, 0}, + {0x1A42, 0x80, 0xFF, 0}, + {0x1A44, 0x702C, 0xFF2C, 0}, + {0x1B0E, 0xF, 0xF, 0}, + {0x1B10, 0x1, 0x1, 0}, + {0x1B14, 0xFFFF, 0xFFFF, 0}, + {0x1B1A, 0x3FFF, 0x3FFF, 0}, + {0x1B32, 0x8, 0x8, 0}, + {0x1B8A, 0x30, 0x8030, 0}, + {0x1B9C, 0x10, 0x8010, 0}, + {0x1BA0, 0x4000, 0x4000, 0}, + {0x1BAE, 0x1410, 0x9C10, 0}, + {0x1BB2, 0x2, 0x2, 0}, + {0x1BC0, 0x10, 0x8010, 0}, + {0x1BD2, 0x13, 0x8013, 0}, + {0x1BE4, 0x10, 0x8010, 0}, + {0x1C0A, 0x10, 0x8010, 0}, + {0x1C1E, 0x10, 0x8010, 0}, + {0x1C30, 0x10, 0x8010, 0}, + {0x1C42, 0x10, 0x8010, 0}, + {0x1C54, 0x32, 0x8033, 0}, + {0x1C66, 0x10, 0x8010, 0}, + {0x1C8A, 0x10, 0x8010, 0}, + {0x1C8E, 0x4000, 0x4000, 0}, + {0x1C9C, 0x10, 0x8010, 0}, + {0x1CAE, 0x10, 0x8010, 0}, + {0x1CC0, 0x10, 0x8010, 0}, + {0x1CD2, 0x33, 0x8033, 0}, + {0x1CE4, 0x33, 0x8033, 0}, + {0x1D0A, 0x10, 0x8010, 0}, + {0x1D1E, 0x10, 0x8010, 0}, + {0x1D22, 0x4000, 0x4000, 0}, + {0x1D30, 0x10, 0x8010, 0}, + {0x1D34, 0x4000, 0x4000, 0}, + {0x1D42, 0x30, 0x8030, 0}, + {0x1D46, 0x4000, 0x4000, 0}, + {0x1D54, 0x30, 0x8030, 0}, + {0x1D66, 0x32, 0x8033, 0}, + {0x1D8A, 0x10, 0x8010, 0}, + {0x1D9C, 0x10, 0x8010, 0}, + {0x1E8A, 0x10, 0x8010, 0}, + {0x1E8E, 0x10, 0x7F, 0}, + {0x1E92, 0xF15, 0x7F7F, 0}, + {0x1EAA, 0x10, 0x8010, 0}, + {0x1EAE, 0x10, 0x7F, 0}, + {0x1EB2, 0xF15, 0x7F7F, 0}, + {0x1F0A, 0x10, 0x8010, 0}, + {0x1F0E, 0x8, 0x7F, 0}, + {0x1F12, 0xF1F, 0x7F7F, 0}, + {0x1F30, 0x10, 0x8010, 0}, + {0x1F34, 0x8, 0x7F, 0}, + {0x1F38, 0xF1F, 0x7F7F, 0}, + {0x200A, 0x8, 0xC, 0}, + {0x202C, 0x8, 0xC, 0}, + {0x208C, 0x100, 0xF00, 0}, + {0x209C, 0x80, 0x1E0, 0}, + /* + * BUCK_VGPU11_OP_MODE/CFG/EN + * Vreq setting for scp usage + */ + {0x15a0, 0x0, 0x1, 11}, + {0x159a, 0x0, 0x1, 11}, + {0x1594, 0x1, 0x1, 11}, +}; + +static const struct pmic_setting lp_setting[] = { + /* Suspend */ + {0x14a0, 0x1, 0x1, 0x0}, + {0x1494, 0x1, 0x1, 0x0}, + {0x149a, 0x1, 0x1, 0x0}, + {0x15a0, 0x1, 0x1, 0x0}, + {0x1594, 0x1, 0x1, 0x0}, + {0x159a, 0x1, 0x1, 0x0}, + {0x1820, 0x1, 0x1, 0x0}, + {0x1814, 0x1, 0x1, 0x0}, + {0x181a, 0x1, 0x1, 0x0}, + {0x18a0, 0x1, 0x1, 0x0}, + {0x1894, 0x1, 0x1, 0x0}, + {0x189a, 0x1, 0x1, 0x0}, + {0x1cac, 0x1, 0x1, 0xa}, + {0x1cb2, 0x1, 0x1, 0x0}, + {0x1cb8, 0x1, 0x1, 0x0}, + {0x1bbe, 0x1, 0x1, 0xa}, + {0x1bc4, 0x1, 0x1, 0x0}, + {0x1bca, 0x1, 0x1, 0x0}, + {0x1d22, 0x1, 0x1, 0xe}, + {0x1d28, 0x0, 0x1, 0xe}, + {0x1c64, 0x1, 0x1, 0xa}, + {0x1c6a, 0x1, 0x1, 0x0}, + {0x1c70, 0x1, 0x1, 0x0}, + {0x1d34, 0x1, 0x1, 0xe}, + {0x1d3a, 0x0, 0x1, 0xe}, + {0x1c88, 0x1, 0x1, 0xa}, + {0x1c8e, 0x1, 0x1, 0x0}, + {0x1c94, 0x1, 0x1, 0x0}, + {0x1b9a, 0x1, 0x1, 0xa}, + {0x1ba0, 0x1, 0x1, 0x0}, + {0x1ba6, 0x1, 0x1, 0x0}, + {0x1d08, 0x1, 0x1, 0xa}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1d9a, 0x1, 0x1, 0xa}, + {0x1da0, 0x1, 0x1, 0x0}, + {0x1da6, 0x1, 0x1, 0x0}, + + /* Deep idle */ + {0x1bbe, 0x1, 0x1, 0xc}, + {0x1bc4, 0x1, 0x1, 0x2}, + {0x1bca, 0x1, 0x1, 0x2}, + {0x1c64, 0x1, 0x1, 0xc}, + {0x1c6a, 0x1, 0x1, 0x2}, + {0x1c70, 0x1, 0x1, 0x2}, + {0x1c88, 0x1, 0x1, 0xc}, + {0x1c8e, 0x1, 0x1, 0x2}, + {0x1c94, 0x1, 0x1, 0x2}, + {0x1b9a, 0x1, 0x1, 0xc}, + {0x1ba0, 0x1, 0x1, 0x2}, + {0x1ba6, 0x1, 0x1, 0x2}, + {0x1d08, 0x1, 0x1, 0xc}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, +}; + +void pmic_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6359p_write_field(init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +void pmic_lp_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(lp_setting); i++) + mt6359p_write_field(lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} diff --git a/src/soc/mediatek/mt8195/pmif_clk.c b/src/soc/mediatek/mt8195/pmif_clk.c new file mode 100644 index 0000000..c6d65ce --- /dev/null +++ b/src/soc/mediatek/mt8195/pmif_clk.c @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/pmif.h> +#include <soc/pmif_clk_common.h> +#include <soc/pmif_sw.h> +#include <soc/pmif_spmi.h> +#include <soc/spm.h> + +/* APMIXED, ULPOSC1_CON0 */ +DEFINE_BITFIELD(OSC1_CALI, 6, 0) +DEFINE_BITFIELD(OSC1_IBAND, 13, 7) +DEFINE_BITFIELD(OSC1_FBAND, 17, 14) +DEFINE_BITFIELD(OSC1_DIV, 23, 18) +DEFINE_BIT(OSC1_CP_EN, 24) +DEFINE_BITFIELD(OSC1_MOD, 26, 25) +DEFINE_BIT(OSC1_DIV2_EN, 27) + +/* APMIXED, ULPOSC1_CON1 */ +DEFINE_BITFIELD(OSC1_RSV1, 7, 0) +DEFINE_BITFIELD(OSC1_RSV2, 15, 8) +DEFINE_BITFIELD(OSC1_32KCALI, 23, 16) +DEFINE_BITFIELD(OSC1_BIAS, 31, 24) + +/* SPM, POWERON_CONFIG_EN */ +DEFINE_BIT(BCLK_CG_EN, 0) +DEFINE_BITFIELD(PROJECT_CODE, 31, 16) + +/* SPM, ULPOSC_CON */ +DEFINE_BIT(ULPOSC_EN, 0) +DEFINE_BIT(ULPOSC_CG_EN, 2) + +/* SCP, SCP_CLK_ON_CTRL */ +DEFINE_BIT(SCP_CLK_ON_CTRL, 1) + +/* INFRA, MODULE_SW_CG */ +DEFINE_BIT(PMIC_CG_TMR, 0) +DEFINE_BIT(PMIC_CG_AP, 1) +DEFINE_BIT(PMIC_CG_MD, 2) +DEFINE_BIT(PMIC_CG_CONN, 3) + +/* INFRA, INFRA_GLOBALCON_RST2 */ +DEFINE_BIT(PMIC_WRAP_SWRST, 0) +DEFINE_BIT(PMICSPMI_SWRST, 14) + +/* INFRA, PMICW_CLOCK_CTRL */ +DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0) + +/* TOPCKGEN, CLK_CFG_9 */ +DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 2, 0) +DEFINE_BIT(PDN_PWRAP_ULPOSC, 0) + +/* TOPCKGEN, CLK_CFG_UPDATE1 */ +DEFINE_BIT(CLK_CFG_UPDATE1, 4) + +static void pmif_ulposc_config(void) +{ + /* ULPOSC1_CON0 */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_DIV2_EN, 0, OSC1_MOD, 0, + OSC1_CP_EN, 0, OSC1_DIV, 0xe, OSC1_FBAND, 0x2, + OSC1_IBAND, 0x52, OSC1_CALI, 0x40); + + /* ULPOSC1_CON1 */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_32KCALI, 0, OSC1_BIAS, 0x40, + OSC1_RSV2, 0, OSC1_RSV1, 0x29); +} + +u32 pmif_get_ulposc_freq_mhz(u32 cali_val) +{ + u32 result = 0; + + /* set calibration value */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val); + udelay(50); + result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK); + + return result / 1000; +} + +static int pmif_init_ulposc(void) +{ + /* calibrate ULPOSC1 */ + pmif_ulposc_config(); + + /* enable spm swinf */ + if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN)) + SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1, + PROJECT_CODE, 0xb16); + + /* turn on ulposc */ + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1); + udelay(100); + SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl, SCP_CLK_ON_CTRL, 1); + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1); + + return pmif_ulposc_cali(FREQ_248MHZ); +} + +int pmif_clk_init(void) +{ + if (pmif_init_ulposc()) + return E_NODEV; + + /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + SET32_BITFIELDS(&mt8195_infracfg_ao->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1, + PMIC_CG_MD, 1, PMIC_CG_CONN, 1); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_9, PDN_PWRAP_ULPOSC, 0, + CLK_PWRAP_ULPOSC_SET, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1); + + /* use ULPOSC1 clock */ + SET32_BITFIELDS(&mt8195_infracfg_ao->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf); + + /* toggle SPI/SPMI sw reset */ + SET32_BITFIELDS(&mt8195_infracfg_ao->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1, + PMIC_WRAP_SWRST, 1); + SET32_BITFIELDS(&mt8195_infracfg_ao->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1, + PMIC_WRAP_SWRST, 1); + + /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + SET32_BITFIELDS(&mt8195_infracfg_ao->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1, + PMIC_CG_MD, 1, PMIC_CG_CONN, 1); + + return 0; +} diff --git a/src/soc/mediatek/mt8195/pmif_spi.c b/src/soc/mediatek/mt8195/pmif_spi.c new file mode 100644 index 0000000..ddb2175 --- /dev/null +++ b/src/soc/mediatek/mt8195/pmif_spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/iocfg.h> +#include <soc/pmif_spi.h> + +/* IOCFG_BM, PWRAP_SPI0_DRIVING */ +DEFINE_BITFIELD(PWRAP_SPI0_DRIVING, 29, 24) +DEFINE_BITFIELD(PWRAP_SPI1_DRIVING, 5, 0) + +void pmif_spi_iocfg(void) +{ + /* Set SoC SPI IO driving strength to 4 mA */ + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA); +} diff --git a/src/soc/mediatek/mt8195/pmif_spmi.c b/src/soc/mediatek/mt8195/pmif_spmi.c new file mode 100644 index 0000000..7323d05 --- /dev/null +++ b/src/soc/mediatek/mt8195/pmif_spmi.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/iocfg.h> +#include <soc/pll.h> +#include <soc/pmif_spmi.h> + +/* IOCFG_BM, DRV_CFG2 */ +DEFINE_BITFIELD(SPMI_SCL, 8, 6) +DEFINE_BITFIELD(SPMI_SDA, 11, 9) +DEFINE_BIT(SPMI_SCL_IN, 20) +DEFINE_BIT(SPMI_SDA_IN, 21) +DEFINE_BIT(SPMI_SCL_PU, 21) +DEFINE_BIT(SPMI_SDA_PD, 22) +DEFINE_BIT(SPMI_SCL_SMT, 25) +DEFINE_BIT(SPMI_SDA_SMT, 26) +DEFINE_BITFIELD(SPMI_TD, 11, 8) +DEFINE_BITFIELD(SPMI_RD, 23, 22) +DEFINE_BITFIELD(SPMI_DRI, 5, 0) + +/* TOPRGU, WDT_SWSYSRST2 */ +DEFINE_BIT(SPMI_MST_RST, 23) +DEFINE_BITFIELD(UNLOCK_KEY, 31, 24) + +/* TOPCKGEN, CLK_CFG_17 */ +DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_MST_INT, 12) +DEFINE_BIT(PDN_SPMI_MST, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE2 */ +DEFINE_BIT(SPMI_MST_CK_UPDATE, 5) + +int spmi_config_master(void) +{ + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_17, + CLK_SPMI_MST_SEL, 0x3, + CLK_SPMI_MST_INT, 0, + PDN_SPMI_MST, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1); + + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + write32(&mtk_spmi_mst->rcs_ctrl, 0x15); + + return 0; +} + +void pmif_spmi_iocfg(void) +{ + SET32_BITFIELDS(&mtk_iocfg_bm->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7); + SET32_BITFIELDS(&mtk_iocfg_bm->ies_cfg1_clr, SPMI_SCL_IN, 0x1); + SET32_BITFIELDS(&mtk_iocfg_bm->ies_cfg1_set, SPMI_SDA_IN, 0x1); + SET32_BITFIELDS(&mtk_iocfg_bm->pu_cfg1_clr, SPMI_SCL_PU, 0x1, + SPMI_SDA_PD, 0x1); + SET32_BITFIELDS(&mtk_iocfg_bm->pd_cfg1_clr, SPMI_SCL_PU, 0x1, + SPMI_SDA_PD, 0x1); + SET32_BITFIELDS(&mtk_iocfg_bm->smt_cfg0_set, SPMI_SCL_SMT, 0x1, + SPMI_SDA_SMT, 0x1); + SET32_BITFIELDS(&mtk_iocfg_bm->tdsel_cfg1_clr, SPMI_TD, 0xF); + SET32_BITFIELDS(&mtk_iocfg_bm->rdsel_cfg0_clr, SPMI_RD, 0x3); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_clr, SPMI_DRI, 0x2D); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_set, SPMI_DRI, 0x12); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 14 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [TEST]: mb/google/brya: Add SKU ID
by Usha P (Code Review) 05 May '21

05 May '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52921 ) Change subject: [TEST]: mb/google/brya: Add SKU ID ...................................................................... [TEST]: mb/google/brya: Add SKU ID Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I313eedccbe85e1c0dcfa6ff8b508761d03554715 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/mainboard.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52921/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index a910cc7..e29c6d5 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -12,7 +12,6 @@ select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 99a060d..7e833ca 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -25,6 +25,12 @@ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } +const char *smbios_system_sku(void) +{ + static const char *sku_str = "sku1"; /* sku{0-1} */ + return sku_str; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, -- To view, visit https://review.coreboot.org/c/coreboot/+/52921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313eedccbe85e1c0dcfa6ff8b508761d03554715 Gerrit-Change-Number: 52921 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Furquan Shaikh (Code Review) 05 May '21

05 May '21

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52725 ) Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... mb/google/puff/var/dooly: enable touchscreen wakeup Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device. BUG=b:186070097 BRANCH=puff TEST=Build and make sure TS works to wakeup suspend/resume. Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/dooly/gpio.c M src/mainboard/google/hatch/variants/dooly/overridetree.cb 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c index 4406c06..5fd88c2 100644 --- a/src/mainboard/google/hatch/variants/dooly/gpio.c +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -12,7 +12,7 @@ /* A19 : GPP_A19 */ PAD_NC(GPP_A19, NONE), /* A20 : TOUCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, PLTRST, LEVEL, INVERT), /* A21 : FPMCU_PCH_BOOT0 */ PAD_NC(GPP_A21, NONE), /* A22 : FPMCU_PCH_INT_L */ diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 69d1428..3d7a4a5 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -327,6 +327,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "100" + register "generic.wake" = "GPE0_DW0_20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 12 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Furquan Shaikh (Code Review) 05 May '21

05 May '21

Attention is currently required from: Sam McNally, Tony Huang, Tim Wawrzynczak, Edward O'Callaghan, Wisley Chen. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52725 ) Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52725/comment/bb3baade_f7df73f5 PS10, Line 9: Follow touchpad to set interrupt gpio to PAD_CFG_GPI_IRQ_WAKE. > Can you please rephrase this as: […] Done. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 11 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 May 2021 04:36:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Tony Huang (Code Review) 05 May '21

05 May '21

Attention is currently required from: Sam McNally, Tim Wawrzynczak, Edward O'Callaghan, Wisley Chen. Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52725 ) Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52725/comment/d1ca2893_f44fda5d PS10, Line 9: Follow touchpad to set interrupt gpio to PAD_CFG_GPI_IRQ_WAKE. > Can you please rephrase this as: […] Done, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 11 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 May 2021 04:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Tony Huang (Code Review) 05 May '21

05 May '21

Attention is currently required from: Sam McNally, Tony Huang, Tim Wawrzynczak, Edward O'Callaghan, Wisley Chen. Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Keith Tzeng, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52725 to look at the new patch set (#11). Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... mb/google/puff/var/dooly: enable touchscreen wakeup Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device. BUG=b:186070097 BRANCH=puff TEST=Build and make sure TS works to wakeup suspend/resume. Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/gpio.c M src/mainboard/google/hatch/variants/dooly/overridetree.cb 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52725/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 11 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021