coreboot-gerrit May 2021

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Krystian Hebel. Hello Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52926 to review the following change. Change subject: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions ...................................................................... nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions Remove obsolete resource assigning functions. Use generic PCI and PCI domain resource allocation functions wherever possible. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 10 insertions(+), 150 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/52926/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e1ff95a..91b1278 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -37,33 +37,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -86,13 +59,6 @@ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - static void f1_write_config32(unsigned int reg, u32 value) { int i; @@ -282,7 +248,7 @@ } -static void read_resources(struct device *dev) +static void nb_read_resources(struct device *dev) { u32 nodeid; struct bus *link; @@ -309,57 +275,6 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; @@ -388,27 +303,16 @@ set_vga_enable_reg(nodeid, sblink); } -static void set_resources(struct device *dev) +static void nb_set_resources(struct device *dev) { unsigned int nodeid; - struct bus *bus; - struct resource *res; /* Find the nodeid */ nodeid = amdfam16_nodeid(dev); create_vga_resource(dev, nodeid); //TODO: do we need this? - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } + pci_dev_set_resources(dev); } static void northbridge_init(struct device *dev) @@ -850,10 +754,11 @@ } static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, + .read_resources = nb_read_resources, + .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, + .ops_pci = &pci_dev_ops_pci, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, }; @@ -922,46 +827,6 @@ .final = fam16_finalize, }; -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - pci_domain_read_resources(dev); -} - -static void domain_enable_resources(struct device *dev) -{ -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -1008,7 +873,7 @@ } #endif -static void domain_set_resources(struct device *dev) +static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -1018,6 +883,8 @@ struct hw_mem_hole_info mem_hole; #endif + pci_domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -1098,12 +965,6 @@ } add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } } static const char *domain_acpi_name(const struct device *dev) @@ -1116,8 +977,7 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Gerrit-Change-Number: 52926 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52761 to look at the new patch set (#2). Change subject: nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4 ...................................................................... nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4 TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6 --- M src/northbridge/amd/pi/00730F01/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/52761/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6 Gerrit-Change-Number: 52761 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52925 to review the following change. Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/mmu_operations.c M src/soc/mediatek/mt8195/soc.c 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52925/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 796c335..f848f7b 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c new file mode 100644 index 0000000..7018093 --- /dev/null +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> +#include <soc/symbols.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index af28dd4..4c98a66 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... mb/google/cherry: configure GPIOs Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/chromeos.c A src/mainboard/google/cherry/gpio.h 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/52924/1 diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index 6f61a82..adb87d0 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -4,6 +4,8 @@ #include <device/mmio.h> #include <soc/gpio.h> +#include "gpio.h" + struct pad_func { u8 pin_id; u8 func; @@ -34,4 +36,5 @@ void bootblock_mainboard_init(void) { nor_set_gpio_pinmux(); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 3f0937f..f606ba3 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -2,10 +2,31 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <gpio.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_GSC_AP_INT); + gpio_output(GPIO_EN_SPK, 0); + gpio_output(GPIO_RESET, 0); +} void fill_lb_gpios(struct lb_gpios *gpios) { - + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_SD_CD.id, ACTIVE_LOW, -1, "SD card detect"}, + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT.id, ACTIVE_LOW, -1, "TPM interrupt"}, + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/cherry/gpio.h b/src/mainboard/google/cherry/gpio.h new file mode 100644 index 0000000..28e1186 --- /dev/null +++ b/src/mainboard/google/cherry/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CHERRY_GPIO_H__ +#define __MAINBOARD_GOOGLE_CHERRY_GPIO_H__ + +#include <soc/gpio.h> + +#define GPIO_EC_AP_INT GPIO(GPIO_04) +#define GPIO_WP GPIO(GPIO_05) +#define GPIO_SD_CD GPIO(I2SO1_D1) +#define GPIO_EC_IN_RW GPIO(DGI_D10) +#define GPIO_GSC_AP_INT GPIO(DGI_D11) +#define GPIO_EN_SPK GPIO(UART1_RTS) +#define GPIO_RESET GPIO(UART1_CTS) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Julius Werner, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51923 ) Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/51923/comment/77376d5d_8a266e15 PS6, Line 62: acpi_is_wakeup_s3 > > I'm not sure if we can detect S3 resume this early […] Ah, I guess because of the power_state thingy? It's something I need to backport from Broadwell to Lynx Point in order to unify both platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Gerrit-Change-Number: 51923 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 05 May 2021 08:30:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Angel Pons, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51923 ) Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... Patch Set 6: (1 comment) File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/51923/comment/fccffa1c_9a43583d PS6, Line 62: acpi_is_wakeup_s3 > I'm not sure if we can detect S3 resume this early Huh, it looks like this would fail on sb/intel. soc/intel does implement this correctly. #yetanothercleanuptodo -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Gerrit-Change-Number: 51923 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 08:26:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Remove bogus SMRAM locking
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Arthur Heymans, Morgan Jang, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51532 ) Change subject: soc/intel/xeon_sp: Remove bogus SMRAM locking ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212 Gerrit-Change-Number: 51532 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 08:21:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52842 ) Change subject: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52842/comment/d42ed35c_affaa1d9 PS5, Line 479: uint8_t bool? -- To view, visit https://review.coreboot.org/c/coreboot/+/52842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Gerrit-Change-Number: 52842 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 08:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Clean up FSP chipset lockdown configuration
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52843 ) Change subject: soc/intel/skylake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52843/comment/579e889a_a683d474 PS6, Line 424: uint8_t bool? -- To view, visit https://review.coreboot.org/c/coreboot/+/52843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Gerrit-Change-Number: 52843 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 08:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Clean up FSP chipset lockdown configuration
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52843 ) Change subject: soc/intel/skylake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: No Skylake boards use FSP lockdown anymore since CB:52094 and CB:52095 got merged. CB:52096 would enforce coreboot lockdown, but it's rather hacky. -- To view, visit https://review.coreboot.org/c/coreboot/+/52843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Gerrit-Change-Number: 52843 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 08:18:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021