coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52895/comment/ed25590e_e2434f41 PS3, Line 13: to make the ramstage postcodes appear in an incremental order. > This should be done in another commit. make sense, will wait for Nico to share his thought on this and then i will split this CL? File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/c52170ce_d4cf87fb PS3, Line 190: POST_BS_WRITE_TABLES > grep says this macro is unused. […] make sense -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 07:54:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 May 2021 07:44:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52895/comment/97bc07fe_3a6b868a PS3, Line 13: to make the ramstage postcodes appear in an incremental order. This should be done in another commit. File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/6efea113_5e1e2d1c PS3, Line 190: POST_BS_WRITE_TABLES grep says this macro is unused. I'd rather renumber (or remove) this instead of POST_PRE_HARDWAREMAIN. File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/f96c04eb_98fc5f45 PS1, Line 191: /** : * \brief Pre call to RAM stage main() : * : * POSTed right before RAM stage main() is called from c_start.S : */ : #define POST_PRE_HARDWAREMAIN 0x7c : : /** : * \brief Entry into coreboot in RAM stage main() : * : * This is the first call in hardwaremain.c. If this code is POSTed, then : * ramstage has successfully loaded and started executing. : */ : #define POST_ENTRY_RAMSTAGE 0x80 > Perfect, done I'd say it doesn't matter. -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 May 2021 07:43:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add mtcmos init support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52882 ) Change subject: soc/mediatek/mt8195: Add mtcmos init support ...................................................................... Patch Set 4: (2 comments) Patchset: PS3: > merge conflict, please rebase . never mind, that's solved. Patchset: PS4: ne -- To view, visit https://review.coreboot.org/c/coreboot/+/52882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Gerrit-Change-Number: 52882 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 May 2021 07:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add mtcmos init support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52882 ) Change subject: soc/mediatek/mt8195: Add mtcmos init support ...................................................................... soc/mediatek/mt8195: Add mtcmos init support Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/spm.h A src/soc/mediatek/mt8195/mtcmos.c 5 files changed, 137 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 0e0e32a..20de4ea 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -8,8 +8,11 @@ u32 pwr_sta_mask; u32 sram_pdn_mask; u32 sram_ack_mask; + u32 caps; }; +#define SCPD_SRAM_ISO (1U << 0) + void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 17a464f..6be7b1c 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -33,6 +33,12 @@ while (read32(pd->pwr_con) & pd->sram_ack_mask) continue; + + if (pd->caps & SCPD_SRAM_ISO) { + setbits32(pd->pwr_con, SRAM_ISOINT_B); + udelay(1); + clrbits32(pd->pwr_con, SRAM_CKISO); + } } void mtcmos_display_power_on(void) diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 0c5b9cf..796c335 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index c90e632..319509a 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -4,8 +4,13 @@ #define SOC_MEDIATEK_MT8195_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <types.h> +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + struct mtk_spm_regs { u32 poweron_config_set; u32 spm_power_on_val0; @@ -528,9 +533,54 @@ u32 spm_pmsr_len_con2; }; +check_member(mtk_spm_regs, pwr_status, 0x016c); +check_member(mtk_spm_regs, audio_pwr_con, 0x0358); check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c); check_member(mtk_spm_regs, ulposc_con, 0x644); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->vppsys0_pwr_con, + .pwr_sta_mask = 0x1 << 11, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vdosys0_pwr_con, + .pwr_sta_mask = 0x1 << 13, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vppsys1_pwr_con, + .pwr_sta_mask = 0x1 << 12, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vdosys1_pwr_con, + .pwr_sta_mask = 0x1 << 14, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->adsp_pwr_con, + .pwr_sta_mask = 0x1 << 10, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + .caps = SCPD_SRAM_ISO, + }, + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = 0x1 << 8, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + #endif /* SOC_MEDIATEK_MT8195_SPM_H */ diff --git a/src/soc/mediatek/mt8195/mtcmos.c b/src/soc/mediatek/mt8195/mtcmos.c new file mode 100644 index 0000000..e194441 --- /dev/null +++ b/src/soc/mediatek/mt8195/mtcmos.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> + +enum { + VPPSYS0_PROT_STEP_6_MASK = 0x00100000, + VPPSYS0_PROT_STEP_5_MASK = 0x0007F8FF, + VPPSYS0_PROT_STEP_4_MASK = 0x00800000, + VPPSYS0_PROT_STEP_3_MASK = 0x01600300, + VPPSYS0_PROT_STEP_2_MASK = 0x80381DC7, + VPPSYS0_PROT_STEP_1_MASK = 0x00000400, + + VDOSYS0_PROT_STEP_5_MASK = 0x00200000, + VDOSYS0_PROT_STEP_4_MASK = 0x3FC00000, + VDOSYS0_PROT_STEP_3_MASK = 0x00000040, + VDOSYS0_PROT_STEP_2_MASK = 0x00800000, + VDOSYS0_PROT_STEP_1_MASK = 0x403E6238, + + VPPSYS1_PROT_STEP_3_MASK = 0x000400C0, + VPPSYS1_PROT_STEP_2_MASK = 0x00800000, + VPPSYS1_PROT_STEP_1_MASK = 0x000001E0, + + VDOSYS1_PROT_STEP_3_MASK = 0x00000400, + VDOSYS1_PROT_STEP_2_MASK = 0x00400000, + VDOSYS1_PROT_STEP_1_MASK = 0xC0000000, + + AUDIO_PROT_STEP_1_MASK = 0x00000600, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VPPSYS0_PROT_STEP_6_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VDOSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VDOSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP_1_MASK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Gerrit-Change-Number: 52882 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add mtcmos init support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52882 ) Change subject: soc/mediatek/mt8195: Add mtcmos init support ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: merge conflict, please rebase . -- To view, visit https://review.coreboot.org/c/coreboot/+/52882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Gerrit-Change-Number: 52882 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 May 2021 07:37:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/console: Fix FSP Notify phase postcodes discrepancy
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52894 ) Change subject: include/console: Fix FSP Notify phase postcodes discrepancy ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Gerrit-Change-Number: 52894 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 07:37:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Move the power domain data under each SoC
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52881 ) Change subject: soc/mediatek: Move the power domain data under each SoC ...................................................................... soc/mediatek: Move the power domain data under each SoC In follow-up patches, we need to set multiple power domains to power on the display and audio on MT8195. Move the power domain data under each SoC and make power_on() API to support multiple settings. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52881 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h 5 files changed, 71 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index d8cb9f5..0e0e32a 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -3,6 +3,13 @@ #ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__ #define __SOC_MEDIATEK_COMMON_MTCMOS_H__ +struct power_domain_data { + void *pwr_con; + u32 pwr_sta_mask; + u32 sram_pdn_mask; + u32 sram_ack_mask; +}; + void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index cfd148c..17a464f 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,16 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <delay.h> #include <device/mmio.h> -#include <soc/mtcmos.h> #include <soc/spm.h> -struct power_domain_data { - void *pwr_con; - u32 pwr_sta_mask; - u32 sram_pdn_mask; - u32 sram_ack_mask; -}; - enum { SRAM_ISOINT_B = 1U << 6, SRAM_CKISO = 1U << 5, @@ -44,24 +37,16 @@ void mtcmos_display_power_on(void) { - static const struct power_domain_data disp = { - .pwr_con = &mtk_spm->dis_pwr_con, - .pwr_sta_mask = DISP_PWR_STA_MASK, - .sram_pdn_mask = DISP_SRAM_PDN_MASK, - .sram_ack_mask = DISP_SRAM_ACK_MASK, - }; + int i; - mtcmos_power_on(&disp); + for (i = 0; i < ARRAY_SIZE(disp); i++) + mtcmos_power_on(&disp[i]); } void mtcmos_audio_power_on(void) { - static const struct power_domain_data audio = { - .pwr_con = &mtk_spm->audio_pwr_con, - .pwr_sta_mask = AUDIO_PWR_STA_MASK, - .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, - .sram_ack_mask = AUDIO_SRAM_ACK_MASK, - }; + int i; - mtcmos_power_on(&audio); + for (i = 0; i < ARRAY_SIZE(audio); i++) + mtcmos_power_on(&audio[i]); } diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index efc04d1..64b33c8 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -4,6 +4,7 @@ #define __SOC_MEDIATEK_MT8173_SPM_H__ #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <stddef.h> enum { @@ -152,4 +153,22 @@ static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 327355a..d5663be 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <types.h> /* SPM READ/WRITE CFG */ @@ -580,4 +581,22 @@ int spm_init(void); +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* SOC_MEDIATEK_MT8183_SPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 8f69bf7..d99ca65 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <stdint.h> #include <types.h> @@ -674,4 +675,22 @@ int spm_init(void); +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* SOC_MEDIATEK_MT8192_SPM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 Gerrit-Change-Number: 52881 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/cherry: Add NOR-Flash support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52872 ) Change subject: mb/google/cherry: Add NOR-Flash support ...................................................................... mb/google/cherry: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52872 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/bootblock.c 3 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 8c7c093..bf46532 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -22,4 +22,10 @@ config MAINBOARD_PART_NUMBER string default "Cherry" if BOARD_GOOGLE_CHERRY + +# On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 endif diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index 4831a39..a1aa2fd 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += memlayout.ld +bootblock-y += bootblock.c bootblock-y += chromeos.c verstage-y += memlayout.ld diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c new file mode 100644 index 0000000..6f61a82 --- /dev/null +++ b/src/mainboard/google/cherry/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/mmio.h> +#include <soc/gpio.h> + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} + +static void nor_set_gpio_pinmux(void) +{ + const struct pad_func *ptr = NULL; + + /* GPIO 140 ~ 143 */ + struct pad_func nor_pinmux[] = { + PAD_FUNC(SPIM2_CSB, SPINOR_CS), + PAD_FUNC(SPIM2_CLK, SPINOR_CK), + PAD_FUNC(SPIM2_MO, SPINOR_IO0), + PAD_FUNC(SPIM2_MI, SPINOR_IO1), + }; + + ptr = nor_pinmux; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { + gpio_set_pull((gpio_t){.id = ptr[i].pin_id}, + GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + } +} + +void bootblock_mainboard_init(void) +{ + nor_set_gpio_pinmux(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf Gerrit-Change-Number: 52872 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add NOR-Flash support
by Hung-Te Lin (Code Review) 05 May '21

05 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52875 ) Change subject: soc/mediatek/mt8195: Add NOR-Flash support ...................................................................... soc/mediatek/mt8195: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/symbols.h M src/soc/mediatek/mt8195/spi.c 4 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index 76329cd..bed3e04 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -17,4 +17,11 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config FLASH_DUAL_READ + bool + default y + help + When this option is enabled, the flash controller provides the ability + to dual read mode. + endif diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 04f4572..0c5b9cf 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) bootblock-y += bootblock.c +bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c @@ -9,6 +10,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c @@ -17,6 +19,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c +romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -30,6 +33,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c ramstage-y += emi.c +ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8195/include/soc/symbols.h b/src/soc/mediatek/mt8195/include/soc/symbols.h new file mode 100644 index 0000000..76d9c6d --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8195_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8195_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8195_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index bc02aa0..cfa52c4 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -3,6 +3,7 @@ #include <assert.h> #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/flash_controller_common.h> #include <soc/gpio.h> #include <soc/spi.h> @@ -93,6 +94,7 @@ static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { @@ -103,6 +105,8 @@ }, { .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Gerrit-Change-Number: 52875 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021