coreboot-gerrit May 2021

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Change in coreboot[master]: [TOTEST]sb/intel/common: Move sleep type clearing into cbmem init
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52931 ) Change subject: [TOTEST]sb/intel/common: Move sleep type clearing into cbmem init ...................................................................... [TOTEST]sb/intel/common: Move sleep type clearing into cbmem init Change-Id: I9d4093f230952aea5a2b3a65d411574a4bcecf72 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmclib.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/52931/1 diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index a5b50a6..e02bc4a 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> #include <stdint.h> #include <acpi/acpi.h> #include <arch/io.h> @@ -89,3 +90,11 @@ return acpi_get_sleep_type() == ACPI_S3; } + +static void clear_sleep_type(int unused) +{ + uint32_t pm1_cnt = read_pmbase32(PM1_CNT); + write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(clear_sleep_type); diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 5bc0ef1..4d207d6 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -19,11 +19,8 @@ if (pm1_sts & WAK_STS) { /* Read PM1_CNT[12:10] to determine which Sx state */ pm1_cnt = read_pmbase32(PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { - /* Clear SLP_TYPE. */ - write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) is_s3 = 1; - } } if (is_s3) { if (!acpi_s3_resume_allowed()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4093f230952aea5a2b3a65d411574a4bcecf72 Gerrit-Change-Number: 52931 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Fix platform_is_resuming()
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52930 ) Change subject: sb/intel/common: Fix platform_is_resuming() ...................................................................... sb/intel/common: Fix platform_is_resuming() platform_is_resuming() was using the wrong register (PM1_STS) to figure out if the platform was resuming (PM1_CNT). Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/pmbase.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/52930/1 diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index bbd2c25..a5b50a6 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -87,5 +87,5 @@ if (!(reg16 & WAK_STS)) return 0; - return acpi_sleep_from_pm1(reg16) == ACPI_S3; + return acpi_get_sleep_type() == ACPI_S3; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Gerrit-Change-Number: 52930 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Implement acpi_is_wakeup_s3()
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52929 ) Change subject: sb/intel/common: Implement acpi_is_wakeup_s3() ...................................................................... sb/intel/common: Implement acpi_is_wakeup_s3() acpi_is_wakeup_s3() requires acpi_get_sleep_type(). Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/pmbase.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/52929/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index adacc25..c468d5c 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -15,6 +15,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2655882..bbd2c25 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -75,6 +75,11 @@ return inb(lpc_get_pmbase() + addr); } +int acpi_get_sleep_type(void) +{ + return acpi_sleep_from_pm1(read_pmbase32(PM1_CNT)); +} + int platform_is_resuming(void) { u16 reg16 = read_pmbase16(PM1_STS); -- To view, visit https://review.coreboot.org/c/coreboot/+/52929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Gerrit-Change-Number: 52929 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/cpu/x86/smm: remove debug message; not thread safe
by Nico Huber (Code Review) 05 May '21

05 May '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52518 ) Change subject: src/cpu/x86/smm: remove debug message; not thread safe ...................................................................... src/cpu/x86/smm: remove debug message; not thread safe This patch removes a call to console_init() and debug print message since the code is not thread safe. This prevents system hangs (soft hangs) while in SMM if user drops in a new SOC with more cores or another socket or as a result of bad configuration. Console is already initialized after the lock has been acquired so this does not affect any other functionality. Tested on DeltaLake mainboard with SMM enabled and 52 CPU threads. Change-Id: I7e8af35d1cde78b327144b6a9da528ae7870e874 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52518 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/smm/smm_module_handler.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f7cf928..0c0de78 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -132,9 +132,7 @@ gnvs = (void *)(uintptr_t)smm_runtime.gnvs_ptr; if (cpu >= CONFIG_MAX_CPUS) { - console_init(); - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); + /* Do not log messages to console here, it is not thread safe */ return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e8af35d1cde78b327144b6a9da528ae7870e874 Gerrit-Change-Number: 52518 Gerrit-PatchSet: 6 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add GPIO driver
by Paul Menzel (Code Review) 05 May '21

05 May '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52598 ) Change subject: soc/mediatek/mt8195: Add GPIO driver ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Could you please write more elaborate commit messages? -- To view, visit https://review.coreboot.org/c/coreboot/+/52598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Gerrit-Change-Number: 52598 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: JG Poxu <jg_poxu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 05 May 2021 09:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Nico Huber (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (3 comments) Patchset: PS3: I only use post codes about once every 3 years, so I don't mind any changes. I didn't notice that the other definition is unused, but agree to what Angel says. I left two random thoughts anyway :) File src/arch/x86/c_start.S: https://review.coreboot.org/c/coreboot/+/52895/comment/e558fcb2_a5629a1a PS3, Line 92: post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ NB. I once worked on another project with similar defines for status codes and comments with their values. This is generally hard to main- tain and very confusing if updating a comment was missed. The solution I came up with was to make the codes part of the identifier, e.g. #define POST_PRE_HARDWAREMAIN_6e 0x6e This way no comment is needed, and the compiler would notice if some place isn't updated. What do you think? File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/8508bd4e_644c0f43 PS3, Line 120: #define POST_ENTRY_RAMSTAGE 0x6f When I first read the patch, I thought this is out of order. "entry ramstage" made me think this is the real entry (in assembler). Maybe it could be renamed to `POST_ENTRY_HARDWAREMAIN`? -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Paul Menzel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52924/comment/df8c13ef_3bfe1c9e PS1, Line 8: Please elaborate, what GPIOs are configured, and where you got this from. -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:20:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Paul Menzel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52925/comment/bf6687e2_e966fbd8 PS1, Line 8: Please add why this is needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52922 to look at the new patch set (#2). Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation Do not use get_dram_base_mask to calculate system DRAM limits. Shift operation around values operating on base and mask were causing overflows and thus incorrect system DRAM limit. Another function returning base and limit in KiB has been developed to avoid data loss. TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian with Linux 4.14 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 4 files changed, 136 insertions(+), 155 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/52922/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52927 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Report missing resources ...................................................................... nb/amd/pi/00730F01/northbridge.c: Report missing resources Not all resources were being reported, add them. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 38 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/52927/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 91b1278..718dc18 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -248,6 +248,30 @@ } +static void add_fixed_resources(struct device *dev, int index) +{ + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM + * 0xe0000 - 0xfffff: SeaBIOS, if used + */ + mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + + if (fx_devs == 0) + get_fx_devs(); + + /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ + if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ + resource_t basek, limitk; + if (!get_dram_base_limit(0, &basek, &limitk)) + return; + mmio_resource(dev, index++, limitk, 16*1024); + } +} + static void nb_read_resources(struct device *dev) { u32 nodeid; @@ -273,6 +297,8 @@ res->base = IO_APIC2_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + add_fixed_resources(dev, 0); } static void create_vga_resource(struct device *dev, unsigned int nodeid) @@ -876,30 +902,15 @@ static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; - u32 pci_tolm; int i, idx; - struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; #endif pci_domain_read_resources(dev); - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); + /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ + mmio_basek = bsp_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -925,16 +936,19 @@ sizek = limitk - basek; - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); + printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", + i, basek, limitk, sizek); + /* see if we need a hole from 0xa0000 to 0xfffff */ + if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { + ram_resource(dev, (idx | i), basek, (0xa0000 >> 10) - basek); + idx += 0x10; + basek = 0x100000 >> 10; + sizek = limitk - basek; } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", + i, basek, limitk, sizek); /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Gerrit-Change-Number: 52927 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021