coreboot-gerrit May 2021

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Rex-BC Chen, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#55) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/… [View More]

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52925 to look at the new patch set (#3). Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure … [View More]

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52924 to look at the new patch set (#2). Change subject: mb/google/cherry: configure GPIOs ...................................................................... mb/google/cherry: configure GPIOs Configure Chromebook specific GPIO. Including … [View More]

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/c_start.S: https://review.coreboot.org/c/coreboot/+/52895/comment/2c4f98d5_43fc2fc6 PS3, Line 92: post_code(… [View More]

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Change in coreboot[master]: sb/intel/common: Fix platform_is_resuming()
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52930 ) Change subject: sb/intel/common: Fix platform_is_resuming() ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings … [View More]

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52925/comment/b623cff1_7ceedfb7 PS1, Line 8: > Please add why this … [View More]

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Rex-BC Chen, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#54) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/… [View More]

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52925 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure … [View More]

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Angel Pons, Andrey Petrov, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52933 ) Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... lib/romstage_handoff.c: Initialize using a cbmem hook This reduces platform boilplate code. Change-Id: … [View More]I93abf33a6eb055eeaba1fed5042387822de1aa20 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/romstage_handoff.h M src/lib/romstage_handoff.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage.c 15 files changed, 7 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/1 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef..483e446 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <halt.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <smp/node.h> #include <string.h> #include <timestamp.h> @@ -79,8 +78,6 @@ halt(); } - romstage_handoff_init(cb->s3resume); - postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 1befc47..e307190 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -13,7 +13,6 @@ #include <fsp/romstage.h> #include <mrc_cache.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <smbios.h> #include <stage_cache.h> #include <string.h> @@ -87,12 +86,6 @@ /* Save DIMM information */ if (!s3wake) mainboard_save_dimm_info(params); - - /* Create romstage handof information */ - if (romstage_handoff_init( - params->power_state->prev_sleep_state == ACPI_S3) < 0) - /* FIXME: A "system" reset is likely enough: */ - full_reset(); } void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index bbc26bc..c5e4cad 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -14,7 +14,6 @@ #include <memrange.h> #include <mrc_cache.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <string.h> #include <symbols.h> #include <timestamp.h> @@ -77,9 +76,6 @@ die("Failed to accommodate FSP reserved memory request!\n"); save_memory_training_data(s3wake, fsp_version); - - /* Create romstage handof information */ - romstage_handoff_init(s3wake); } static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index d0e30b4..f7c43f5 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -2,9 +2,6 @@ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H -/* Returns 0 if initialized. Else < 0 if handoff structure not added. */ -int romstage_handoff_init(int is_s3_resume); - /* Return 1 if resuming or 0 if not. */ int romstage_handoff_is_resume(void); diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index faa2bc9..056322c 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -39,20 +39,22 @@ return handoff; } -int romstage_handoff_init(int is_s3_resume) +static void romstage_handoff_init(int is_s3_resume) { struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); - if (handoff == NULL) - return -1; + if (handoff == NULL) { + printk(BIOS_ERR, "Initializing romstage handoff failed!"); + return; + } handoff->s3_resume = is_s3_resume; - - return 0; } +ROMSTAGE_CBMEM_INIT_HOOK(romstage_handoff_init); + int romstage_handoff_is_resume(void) { static int once, s3_resume; diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index e95c37c..7220b03 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> -#include <romstage_handoff.h> #include <console/console.h> #include <device/pci_ops.h> #include <acpi/acpi.h> @@ -94,7 +93,5 @@ cbmem_initted = !cbmem_recovery(s3resume); - romstage_handoff_init(cbmem_initted && s3resume); - printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index e8984df..efce119 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -5,7 +5,6 @@ #include <device/mmio.h> #include <elog.h> #include <cpu/x86/lapic.h> -#include <romstage_handoff.h> #include <security/intel/txt/txt.h> #include <security/intel/txt/txt_register.h> #include <northbridge/intel/haswell/haswell.h> @@ -60,8 +59,6 @@ haswell_unhide_peg(); - romstage_handoff_init(s3resume); - mb_late_romstage_setup(); post_code(0x3f); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b9c9441..9ca1c07 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -7,7 +7,6 @@ #include <device/pci_ops.h> #include <device/pci.h> #include <option.h> -#include <romstage_handoff.h> #include <types.h> #include "i945.h" @@ -800,8 +799,6 @@ int cbmem_was_initted; cbmem_was_initted = !cbmem_recovery(s3resume); - - romstage_handoff_init(cbmem_was_initted && s3resume); } void i945_late_initialization(int s3resume) diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index cf850d9..8cdea7f 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -7,7 +7,6 @@ #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> -#include <romstage_handoff.h> #include "ironlake.h" #include <arch/romstage.h> #include <device/pci_def.h> @@ -57,6 +56,4 @@ timestamp_add_now(TS_AFTER_INITRAM); intel_early_me_status(); - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 0ee7191..aaced44 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <cf9_reset.h> -#include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -69,6 +68,4 @@ /* Failed S3 resume, reset to come up cleanly */ system_reset(); } - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 9e1cee89..d4ddf0a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -4,7 +4,6 @@ #include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> -#include <romstage_handoff.h> #include "sandybridge.h" #include <arch/romstage.h> #include <device/pci_def.h> @@ -75,6 +74,4 @@ northbridge_romstage_finalize(); post_code(0x3f); - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index e6416ed..d93da01 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> -#include <romstage_handoff.h> #include <arch/romstage.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -44,6 +43,4 @@ x4x_late_init(); printk(BIOS_DEBUG, "x4x late init complete\n"); - - romstage_handoff_init(s3_resume); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d21..305096e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <elog.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> @@ -114,8 +113,6 @@ post_code(0x43); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); - if (romstage_handoff_init(s3_resume)) - printk(BIOS_ERR, "Failed to set romstage handoff data\n"); if (CONFIG(SMM_TSEG)) smm_list_regions(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dbf4afc..49380d9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cbmem.h> #include <elog.h> -#include <romstage_handoff.h> #include <string.h> #include <timestamp.h> #include <soc/iomap.h> @@ -116,6 +115,4 @@ raminit(&mp, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); - - romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 0ba6258..3a8d42a 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> -#include <romstage_handoff.h> #include <soc/me.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -86,7 +85,5 @@ setup_sdram_meminfo(&pei_data); - romstage_handoff_init(s3resume); - mainboard_post_raminit(s3resume); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: nb/intel/*: Use acpi_is_wake_s3
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52932 ) Change subject: nb/intel/*: Use acpi_is_wake_s3 ...................................................................... nb/intel/*: Use acpi_is_wake_s3 Change-Id: If71286bde340933e9e102daecb56ae34908fd5f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/romstage.c M … [View More]src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/southbridge/intel/common/Makefile.inc D src/southbridge/intel/common/pmclib.c D src/southbridge/intel/common/pmclib.h 10 files changed, 7 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/52932/1 diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a..e95c37c 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -10,7 +10,6 @@ #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/gpio.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmutil.h> #include <string.h> @@ -59,7 +58,7 @@ dmibar_clrbits16(0x204, 3 << 10); /* Check for S3 resume. */ - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); /* RAM initialization */ enter_raminit_or_reset(); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c79..e8984df 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -10,7 +10,6 @@ #include <security/intel/txt/txt_register.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/lynxpoint/pch.h> void __weak mb_late_romstage_setup(void) @@ -30,7 +29,7 @@ haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - const int s3resume = southbridge_detect_s3_resume(); + const int s3resume = acpi_is_wakeup_s3(); elog_boot_notify(s3resume); diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d6..1274bfc 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -7,7 +7,6 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> __weak void mainboard_lpc_decode(void) { @@ -44,7 +43,7 @@ i82801gx_early_init(); i945_early_initialization(); - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); mainboard_pre_raminit_config(s3resume); diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..cf850d9 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -14,7 +14,6 @@ #include <device/device.h> #include <northbridge/intel/ironlake/chip.h> #include <northbridge/intel/ironlake/raminit.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> @@ -34,7 +33,7 @@ early_pch_init(); - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); if (s3resume) { u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); if (!(reg8 & 0x20)) { diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420c..0ee7191 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -7,7 +7,6 @@ #include <cf9_reset.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> #include "raminit.h" @@ -39,7 +38,7 @@ post_code(0x30); - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); if (s3resume) { boot_path = BOOT_PATH_RESUME; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9..9e1cee89 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmclib.h> #include <elog.h> __weak void mainboard_early_init(int s3_resume) @@ -50,7 +49,7 @@ systemagent_early_init(); printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); elog_boot_notify(s3resume); diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 1695ddd..e6416ed 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <romstage_handoff.h> -#include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -32,7 +31,7 @@ x4x_early_init(); - s3_resume = southbridge_detect_s3_resume(); + s3_resume = acpi_is_wakeup_s3(); mb_pre_raminit_setup(s3_resume); if (s3_resume) diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c468d5c..56ab596 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -15,9 +15,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c - ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c deleted file mode 100644 index 4d207d6..0000000 --- a/src/southbridge/intel/common/pmclib.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <acpi/acpi.h> -#include <console/console.h> - -#include "pmclib.h" -#include "pmbase.h" -#include "pmutil.h" - -int southbridge_detect_s3_resume(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = read_pmbase16(PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = read_pmbase32(PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) - is_s3 = 1; - } - if (is_s3) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); - return 0; - } - - printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); - } - - return is_s3; -} diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h deleted file mode 100644 index fd87a01..0000000 --- a/src/southbridge/intel/common/pmclib.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef INTEL_COMMON_PMCLIB_H -#define INTEL_COMMON_PMCLIB_H - -/* - * Returns 1 if platform was in ACPI S3 power state and CONFIG(HAVE_ACPI_RESUME) - * is enabled else returns 0. - */ -int southbridge_detect_s3_resume(void); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/52932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If71286bde340933e9e102daecb56ae34908fd5f5 Gerrit-Change-Number: 52932 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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coreboot-gerrit May 2021