Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Angel Pons, Andrey Petrov, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52933 )
Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ......................................................................
lib/romstage_handoff.c: Initialize using a cbmem hook
This reduces platform boilplate code.
Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/romstage_handoff.h M src/lib/romstage_handoff.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage.c 15 files changed, 7 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/1
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef..483e446 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <halt.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <smp/node.h> #include <string.h> #include <timestamp.h> @@ -79,8 +78,6 @@ halt(); }
- romstage_handoff_init(cb->s3resume); - postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 1befc47..e307190 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -13,7 +13,6 @@ #include <fsp/romstage.h> #include <mrc_cache.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <smbios.h> #include <stage_cache.h> #include <string.h> @@ -87,12 +86,6 @@ /* Save DIMM information */ if (!s3wake) mainboard_save_dimm_info(params); - - /* Create romstage handof information */ - if (romstage_handoff_init( - params->power_state->prev_sleep_state == ACPI_S3) < 0) - /* FIXME: A "system" reset is likely enough: */ - full_reset(); }
void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index bbc26bc..c5e4cad 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -14,7 +14,6 @@ #include <memrange.h> #include <mrc_cache.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <string.h> #include <symbols.h> #include <timestamp.h> @@ -77,9 +76,6 @@ die("Failed to accommodate FSP reserved memory request!\n");
save_memory_training_data(s3wake, fsp_version); - - /* Create romstage handof information */ - romstage_handoff_init(s3wake); }
static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index d0e30b4..f7c43f5 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -2,9 +2,6 @@ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H
-/* Returns 0 if initialized. Else < 0 if handoff structure not added. */ -int romstage_handoff_init(int is_s3_resume); - /* Return 1 if resuming or 0 if not. */ int romstage_handoff_is_resume(void);
diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index faa2bc9..056322c 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -39,20 +39,22 @@ return handoff; }
-int romstage_handoff_init(int is_s3_resume) +static void romstage_handoff_init(int is_s3_resume) { struct romstage_handoff *handoff;
handoff = romstage_handoff_find_or_add();
- if (handoff == NULL) - return -1; + if (handoff == NULL) { + printk(BIOS_ERR, "Initializing romstage handoff failed!"); + return; + }
handoff->s3_resume = is_s3_resume; - - return 0; }
+ROMSTAGE_CBMEM_INIT_HOOK(romstage_handoff_init); + int romstage_handoff_is_resume(void) { static int once, s3_resume; diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index e95c37c..7220b03 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> -#include <romstage_handoff.h> #include <console/console.h> #include <device/pci_ops.h> #include <acpi/acpi.h> @@ -94,7 +93,5 @@
cbmem_initted = !cbmem_recovery(s3resume);
- romstage_handoff_init(cbmem_initted && s3resume); - printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index e8984df..efce119 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -5,7 +5,6 @@ #include <device/mmio.h> #include <elog.h> #include <cpu/x86/lapic.h> -#include <romstage_handoff.h> #include <security/intel/txt/txt.h> #include <security/intel/txt/txt_register.h> #include <northbridge/intel/haswell/haswell.h> @@ -60,8 +59,6 @@
haswell_unhide_peg();
- romstage_handoff_init(s3resume); - mb_late_romstage_setup();
post_code(0x3f); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b9c9441..9ca1c07 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -7,7 +7,6 @@ #include <device/pci_ops.h> #include <device/pci.h> #include <option.h> -#include <romstage_handoff.h> #include <types.h>
#include "i945.h" @@ -800,8 +799,6 @@ int cbmem_was_initted;
cbmem_was_initted = !cbmem_recovery(s3resume); - - romstage_handoff_init(cbmem_was_initted && s3resume); }
void i945_late_initialization(int s3resume) diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index cf850d9..8cdea7f 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -7,7 +7,6 @@ #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> -#include <romstage_handoff.h> #include "ironlake.h" #include <arch/romstage.h> #include <device/pci_def.h> @@ -57,6 +56,4 @@ timestamp_add_now(TS_AFTER_INITRAM);
intel_early_me_status(); - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 0ee7191..aaced44 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <cf9_reset.h> -#include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -69,6 +68,4 @@ /* Failed S3 resume, reset to come up cleanly */ system_reset(); } - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 9e1cee89..d4ddf0a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -4,7 +4,6 @@ #include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> -#include <romstage_handoff.h> #include "sandybridge.h" #include <arch/romstage.h> #include <device/pci_def.h> @@ -75,6 +74,4 @@ northbridge_romstage_finalize();
post_code(0x3f); - - romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index e6416ed..d93da01 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h> -#include <romstage_handoff.h> #include <arch/romstage.h>
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -44,6 +43,4 @@
x4x_late_init(); printk(BIOS_DEBUG, "x4x late init complete\n"); - - romstage_handoff_init(s3_resume); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d21..305096e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <elog.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> @@ -114,8 +113,6 @@ post_code(0x43); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); - if (romstage_handoff_init(s3_resume)) - printk(BIOS_ERR, "Failed to set romstage handoff data\n");
if (CONFIG(SMM_TSEG)) smm_list_regions(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dbf4afc..49380d9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cbmem.h> #include <elog.h> -#include <romstage_handoff.h> #include <string.h> #include <timestamp.h> #include <soc/iomap.h> @@ -116,6 +115,4 @@ raminit(&mp, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM); - - romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 0ba6258..3a8d42a 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> -#include <romstage_handoff.h> #include <soc/me.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -86,7 +85,5 @@
setup_sdram_meminfo(&pei_data);
- romstage_handoff_init(s3resume); - mainboard_post_raminit(s3resume); }
-
Arthur Heymans (Code Review)