coreboot-gerrit May 2021

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Change in coreboot[master]: tests: Enable config override for tests
by Jakub Czapiga (Code Review) 05 May '21

05 May '21

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... tests: Enable config override for tests Some tests require to change kconfig symbols values to cover the code. This patch enables one to set these vaues using <test-name>-config variable. Example for integer values. timestamp-test-config += CONFIG_HAVE_MONOTONIC_TIMER=1 Example for string values. Notice escaped quotes. spd_cache-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"SPD_CACHE_FMAP_NAME\" Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 --- M tests/Makefile.inc 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/52937/1 diff --git a/tests/Makefile.inc b/tests/Makefile.inc index fd3cd9f..1172b8c 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -11,7 +11,7 @@ TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx TEST_DOTCONFIG = $(testobj)/.config -TEST_KCONFIG_AUTOHEADER := $(testobj)/config.h +TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd TEST_KCONFIG_SPLITCONFIG := $(testobj)/config @@ -52,7 +52,7 @@ TEST_LDFLAGS += -no-pie # Extra attributes for unit tests, declared per test -attributes:= srcs cflags mocks stage +attributes:= srcs cflags config mocks stage stages:= decompressor bootblock romstage smm verstage stages+= ramstage rmodule postcar libagesa @@ -83,6 +83,25 @@ # Create actual targets for unit test binaries # $1 - test name define TEST_CC_template + +# Generate custom config.h redefining given symbols +$(eval $(1)-config-file := $(obj)/$(1)/config.h) +$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) +$($(1)-config-file): + mkdir -p $$(dir $$@) + printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@ + printf '#include <config.src.h>\n\n' >> $$@ + for kv in $$($(1)-config); do \ + key="`echo $$$$kv | cut -d '=' -f -1`"; \ + value="`echo $$$$kv | cut -d '=' -f 2-`"; \ + printf '#ifdef %s\n' "$$$$key" >> $$@; \ + printf '#undef %s\n' "$$$$key" >> $$@; \ + printf '#endif\n' >> $$@; \ + printf '#define %s %s\n\n' "$$$$key" "$$$$value" >> $$@; \ + done + +$($(1)-objs): TEST_CFLAGS += -I$(dir $($(1)-config-file)) +$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $($(1)-config-file) $($(1)-objs): TEST_CFLAGS+= \ -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ $($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER) -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52780 ) Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4 ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Will try to split it, hopefully the "cosmetic" changes won't break anything. Nico, hope this split will help others review. Is it now better separated? -- To view, visit https://review.coreboot.org/c/coreboot/+/52780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31 Gerrit-Change-Number: 52780 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:55:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Update pirika device tree
by Alex1 Kao (Code Review) 05 May '21

05 May '21

Alex1 Kao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52936 ) Change subject: mb/google/dedede: Update pirika device tree ...................................................................... mb/google/dedede: Update pirika device tree Update pirika device tree override to match schematics. BUG=b:184157747 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d --- M src/mainboard/google/dedede/variants/pirika/overridetree.cb 1 file changed, 142 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/52936/1 diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb index 404024b..b74e31e 100644 --- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb +++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb @@ -9,9 +9,6 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -21,22 +18,154 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + }" + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "tcc_offset" = "8" # TCC of 97C + device domain 0 on - device pci 15.0 on end + device pci 04.0 on + # Default DPTF Policy for all Dedede boards if not overridden + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 67, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 62, 1000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 58, 1000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 40, 1000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 98, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN) + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 4500, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Vcore"" + register "options.tsr[2].desc" = ""Ambient"" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2702"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 15.1 off end + device pci 15.2 off end + device pci 15.3 off end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on + probe AUDIO_AMP RT1015_I2C + probe AUDIO_AMP UNPROVISIONED + end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on + probe AUDIO_AMP RT1015_I2C + probe AUDIO_AMP UNPROVISIONED + end + end + end + device pci 1f.3 on + chip drivers/generic/alc1015 + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on + probe AUDIO_AMP RT1015P_AUTO + end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/52936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d Gerrit-Change-Number: 52936 Gerrit-PatchSet: 1 Gerrit-Owner: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard: Add Synology DS918+
by build bot (Jenkins) (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Name of user not set #1003506, Martin Roth, Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52594 ) Change subject: mainboard: Add Synology DS918+ ...................................................................... Patch Set 7: (62 comments) File src/mainboard/synology/ds918plus/early_gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/6134c66d_d472b09e PS7, Line 40: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/7b788d59_92848f66 PS7, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/e23c7a52_74c6f0f9 PS7, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/2ae08a7b_4a3b09d0 PS7, Line 60: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/e3509d39_55c7c27e PS7, Line 61: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters File src/mainboard/synology/ds918plus/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/ad11ad7f_4063cacd PS7, Line 47: PAD_CFG_GPI_APIC_IOS(GPIO_33, DN_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/fcaeea48_f2981615 PS7, Line 52: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/1f719b6c_abe27d53 PS7, Line 53: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/f6601caf_98a1e1d8 PS7, Line 54: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/6ea45fc3_759c1b03 PS7, Line 55: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/2cf4b306_5b1ab2d0 PS7, Line 56: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART1_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/a41d0908_a6d02707 PS7, Line 57: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/cd3617da_0318b69e PS7, Line 58: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART1_RTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/cd0365de_856cb5d1 PS7, Line 59: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* LPSS_UART1_CTS_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/c6f42220_dcb268e3 PS7, Line 85: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/1ea675db_ff2f2d89 PS7, Line 86: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_RSP, DN_20K, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/46da975f_7e7928e3 PS7, Line 102: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/1e2db510_3318e173 PS7, Line 103: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/023580b8_6edbd1d0 PS7, Line 104: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, DN_20K, Tx0RxDCRx0, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/37ea0791_7e356246 PS7, Line 114: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS0, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/78c9fd2f_d7d68d0f PS7, Line 115: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_FS1, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/23902f9e_a1718963 PS7, Line 117: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_RXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/66ad6c40_5836754b PS7, Line 118: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_TXD, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/eeb6500a_bb82d777 PS7, Line 119: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMC_SPI_CLK, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/f0816bec_ea71aed7 PS7, Line 121: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_RESET_B, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/e3942ba7_15a27918 PS7, Line 126: PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_STDBY, NONE, DEEP, OFF, IGNORE, ACPI), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/178b0996_e0cbc4e8 PS7, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_81, DN_20K, DEEP, NF2, TxDRxE, ENPD), /* AVS_I2C4_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/f0b42c5f_2496faa8 PS7, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_DMIC_DATA_2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/12fcecf1_ba24c3c3 PS7, Line 147: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_91, DN_20K, DEEP, NF1, TxDRxE, ENPD), /* AVS_I2S3_SDI */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/cd9fa803_07cfe648 PS7, Line 157: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_CLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/480e657e_039d41c8 PS7, Line 158: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/11170cd6_a6778070 PS7, Line 159: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_FS1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/a18f0aea_df6a40a7 PS7, Line 160: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_RXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/316f669f_25ff80f9 PS7, Line 161: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_0_TXD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/c7a3fe76_da519f97 PS7, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/e251d0fd_778a2773 PS7, Line 178: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/34e1c4ec_289a2d50 PS7, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/30a756c0_fa475908 PS7, Line 180: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/d1c3761e_42967b63 PS7, Line 181: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/f33a4e96_8a176745 PS7, Line 182: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C2_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/c7a64e28_3f5160ca PS7, Line 183: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/26822350_1d439d36 PS7, Line 184: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C3_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/a0f05faa_3816d55b PS7, Line 185: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/44c99523_c040523f PS7, Line 186: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), /* LPSS_I2C4_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/d594c632_04781c32 PS7, Line 187: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_134, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/76cceb46_67cba4fa PS7, Line 188: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_135, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/612450a3_82161408 PS7, Line 189: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_136, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/1d635073_48fa4921 PS7, Line 190: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_137, NONE, DEEP, NF2, IGNORE, ENPU), /* ISH_I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/93d1ba98_ee3edb75 PS7, Line 191: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/33862de1_17009cb9 PS7, Line 192: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), /* LPSS_I2C7_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/93482f5b_97bf91ef PS7, Line 203: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ0_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/c470eead_5239c183 PS7, Line 204: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_210, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ1_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/d5af1070_4567d445 PS7, Line 205: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ2_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/df30d571_0ef92207 PS7, Line 206: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_212, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* PCIE_CLKREQ3_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/199a0861_a98eb9fa PS7, Line 216: PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/ae646f70_b030fbd7 PS7, Line 221: PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 1, DEEP, UP_20K, IGNORE, SAME), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/72c924e7_1f574624 PS7, Line 264: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/ee344b1c_aa8408d5 PS7, Line 265: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/a41364f4_44d61a3f PS7, Line 266: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/f6f3342f_8f183990 PS7, Line 267: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/a4b1db6e_3b9f6f40 PS7, Line 268: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118479): https://review.coreboot.org/c/coreboot/+/52594/comment/9c6cea8f_786da9d9 PS7, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAMEB */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 7 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Name of user not set #1003506 Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 05 May 2021 09:54:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... nb/amd/agesa/family14/northbridge.c: Report missing resources Not all resources were being reported, add them. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 49 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f58fc09..8ea4a96 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -239,19 +239,6 @@ } } -static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) -{ - struct resource *min; - unsigned long mask_match = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - min = 0; - search_bus_resources(bus, mask_match, mask_match, tolm_test, - &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { @@ -280,6 +267,36 @@ } #endif +static void add_fixed_resources(struct device *dev, int index) +{ + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM + * 0xe0000 - 0xfffff: SeaBIOS, if used + */ + mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + + if (fx_devs == 0) + get_fx_devs(); + + /* + * Check if CC6 is enabled (bits [11:0] C6Base). Ff CC6 is not enabled, the base + * must be zero according to BKDG. + */ + if (pci_read_config32(__f4_dev[0], 0x12C) & 0xfff) { + resource_t c6basek; + c6basek = pci_read_config32(__f4_dev[0], 0x12C) & 0xfff; // [35:24] at [11:0] + /* + * Shift left by 24 bits for physical address and the convert to KiB by + * shifting 10 bits left. The C6Base is shifted 14 bits left thus no overflow. + */ + c6basek = c6basek << (24 - 10); + mmio_resource(dev, index++, c6basek, 16*1024); + } +} + static void nb_read_resources(struct device *dev) { u32 nodeid; @@ -300,6 +317,8 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + add_fixed_resources(dev, 0); } #if CONFIG(CONSOLE_VGA_MULTI) @@ -360,9 +379,8 @@ printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); unsigned long mmio_basek; - u32 pci_tolm; + resource_t basek, limitk, sizek; // 4 1T int idx; - struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; @@ -370,21 +388,11 @@ pci_domain_read_resources(dev); - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } + /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ + mmio_basek = bsp_topmem() >> 10; - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) - 1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64 * 1024) - 1); + if (fx_devs == 0) + get_fx_devs(); #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -403,7 +411,6 @@ #endif idx = 0x10; - resource_t basek, limitk, sizek; // 4 1T if (get_dram_base_limit(0, &basek, &limitk)) { sizek = limitk - basek; @@ -411,18 +418,16 @@ printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", basek, limitk, sizek); - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < 640) && (sizek > 768)) { - printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n"); - ram_resource(dev, (idx | 0), basek, 640 - basek); + /* see if we need a hole from 0xa0000 to 0xfffff */ + if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { + ram_resource(dev, idx, basek, (0xa0000 >> 10) - basek); idx += 0x10; - basek = 768; - sizek = limitk - 768; + basek = 0x100000 >> 10; + sizek = limitk - basek; } - printk(BIOS_DEBUG, - "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { @@ -440,16 +445,16 @@ if ((basek + sizek) <= 4 * 1024 * 1024) { sizek = 0; } else { + uint64_t topmem2 = bsp_topmem2(); basek = 4 * 1024 * 1024; - sizek -= (4 * 1024 * 1024 - mmio_basek); + sizek = topmem2 / 1024 - basek; } } - ram_resource(dev, (idx | 0), basek, sizek); + ram_resource(dev, idx, basek, sizek); idx += 0x10; - printk(BIOS_DEBUG, - "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, - mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, + mmio_basek, basek, limitk); } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52934 ) Change subject: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions ...................................................................... nb/amd/agesa/family14/northbridge.c: Use generic allocation functions Remove obsolete resource assigning functions. Use generic PCI and PCI domain resource allocation functions wherever possible. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 14 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4aed96b..f58fc09 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,42 +26,6 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned int fx_devs = 0; -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | - ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max, u32 nodes) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg + 4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -83,13 +47,6 @@ } } -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - static void f1_write_config32(unsigned int reg, u32 value) { int i; @@ -197,7 +154,7 @@ * but we need one index to differ them. So,same node and same * link can have multi range */ - u32 index = get_io_addr_index(nodeid, link); + u32 index = 0; reg = 0x110 + (index << 24) + (4 << 20); // index could be 0, 255 } @@ -233,7 +190,7 @@ * but we need one index to differ them. So,same node and same * link can have multi range */ - u32 index = get_mmio_addr_index(nodeid, link); + u32 index = 0; reg = 0x110 + (index << 24) + (6 << 20); // index could be 0, 63 } @@ -345,55 +302,6 @@ mmconf_resource(dev, MMIO_CONF_BASE); } -static void set_resource(struct device *dev, struct resource *resource, - u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, - rend >> 8); - } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24), - rbase >> 8, rend >> 8, 1); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - #if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -433,8 +341,6 @@ static void nb_set_resources(struct device *dev) { unsigned int nodeid; - struct bus *bus; - struct resource *res; printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); @@ -443,64 +349,13 @@ create_vga_resource(dev, nodeid); - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } + pci_dev_set_resources(dev); } /* Domain/Root Complex related code */ static void domain_read_resources(struct device *dev) { - unsigned int reg; - - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xc0; reg += 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = - new_resource(reg_dev, - IOINDEX(0x1000 + reg, - reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - -static void domain_set_resources(struct device *dev) -{ printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); @@ -513,6 +368,8 @@ u32 reset_memhole = 1; #endif + pci_domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); @@ -597,13 +454,6 @@ printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } - printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } static const char *domain_acpi_name(const struct device *dev) @@ -780,13 +630,13 @@ } static struct device_operations northbridge_operations = { - .read_resources = nb_read_resources, - .set_resources = nb_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .read_resources = nb_read_resources, + .set_resources = nb_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .init = northbridge_init, - .enable = 0,.ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { @@ -804,9 +654,9 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .scan_bus = pci_domain_scan_bus, - .acpi_name = domain_acpi_name, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, }; static struct device_operations cpu_bus_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a Gerrit-Change-Number: 52934 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki. Hello build bot (Jenkins), Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52780 to look at the new patch set (#2). Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4 ...................................................................... northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4 TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31 --- M src/northbridge/amd/agesa/family14/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/52780/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31 Gerrit-Change-Number: 52780 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard: Add Synology DS918+
by Name of user not set (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Name of user not set #1003506, Martin Roth, Angel Pons, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52594 to look at the new patch set (#7). Change subject: mainboard: Add Synology DS918+ ...................................................................... mainboard: Add Synology DS918+ I'm new to coreboot. This port is based on 4.13, this board boots. Tested with tianocore. Can provide serial logs, original Synology's DSM OS works fine with this port. Can run tests on my board. Now works on Master. Things todo: * polish * I211 ethernet chips initialise with 00:11:22:33:44:55 MAC's as in vendor's, is there a better way? * Sata 88SE9215 is gpio controlled, 4 chips, 1 for each sata port. All sata is turned off by default, is there a better way? * 2nd HSUART Serial doesn't work in OS, only in original DSM. Tried all console=ttyS*,115200 and all 'set tty com*' (as per obsd), probably not cb problem. * Freebsd usb stick causes X86 exception, OpenBSD fails to boot at entry point 0x1001000. Both have apl support. log: https://clbin.com/JrurJ * ... Patch set 2 Reformated gpio part and dsdt. Here are serial logs: https://clbin.com/tHOE7 -- Master branch https://clbin.com/wp4R8 -- 4.13 + seabios, same code except 1 include in dsdt https://clbin.com/iUrgJ -- 4.13 + tianocore, same code... Video test: https://schizoden.xyz/videos/watch/816c5a68-af6f-4dd4-8c7e-43d068410822 Patch set 3/4 More gpio reformating, added data.vbt from vendors bios. * trim spare lines on the end, for jenkins sake Patch set 5/6 Removed data.vbt, causes serial to shut off at post 0x98 Fixed cbfs>mem-mapped area from ifwi + MCACHE -400 err -- .fmd Added cmos.layout cmos.default Edited pci-e devices and turned on vtd in devicetree.cb * forgot to remove dptf, which was added as a test. Patch set 7 Fixed ethernet by removing register pcie_rp_clkreq_pin from devicetree Was able to finally replace vendor's bios in my daily NAS's duties Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Signed-off-by: mkjOoB <dump(a)schizoden.xyz> --- A src/mainboard/synology/Kconfig A src/mainboard/synology/Kconfig.name A src/mainboard/synology/ds918plus/Kconfig A src/mainboard/synology/ds918plus/Kconfig.name A src/mainboard/synology/ds918plus/Makefile.inc A src/mainboard/synology/ds918plus/board_info.txt A src/mainboard/synology/ds918plus/bootblock.c A src/mainboard/synology/ds918plus/cmos.default A src/mainboard/synology/ds918plus/cmos.layout A src/mainboard/synology/ds918plus/devicetree.cb A src/mainboard/synology/ds918plus/ds918plus.fmd A src/mainboard/synology/ds918plus/dsdt.asl A src/mainboard/synology/ds918plus/early_gpio.c A src/mainboard/synology/ds918plus/gpio.c A src/mainboard/synology/ds918plus/gpio.h A src/mainboard/synology/ds918plus/mainboard.c A src/mainboard/synology/ds918plus/romstage.c 17 files changed, 633 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52594/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e0819c97a617e5558480e7cdac05e3cff185 Gerrit-Change-Number: 52594 Gerrit-PatchSet: 7 Gerrit-Owner: Name of user not set #1003506 Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Name of user not set #1003506 Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Rex-BC Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52924/comment/ddb2662c_b3c3ea94 PS1, Line 8: > Please elaborate, what GPIOs are configured, and where you got this from. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:46:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/c_start.S: https://review.coreboot.org/c/coreboot/+/52895/comment/58f3a62a_c7764a44 PS3, Line 92: post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ > this is good idea Nico, but it might need lots of code change due to macro renaming ? […] I like the idea. This renaming can and should be done in a separate patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 May 2021 09:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021