Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52934 )
Change subject: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions ......................................................................
nb/amd/agesa/family14/northbridge.c: Use generic allocation functions
Remove obsolete resource assigning functions. Use generic PCI and PCI domain resource allocation functions wherever possible.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 14 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/1
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4aed96b..f58fc09 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,42 +26,6 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned int fx_devs = 0;
-static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | - ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max, u32 nodes) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg + 4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -83,13 +47,6 @@ } }
-static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - static void f1_write_config32(unsigned int reg, u32 value) { int i; @@ -197,7 +154,7 @@ * but we need one index to differ them. So,same node and same * link can have multi range */ - u32 index = get_io_addr_index(nodeid, link); + u32 index = 0; reg = 0x110 + (index << 24) + (4 << 20); // index could be 0, 255 }
@@ -233,7 +190,7 @@ * but we need one index to differ them. So,same node and same * link can have multi range */ - u32 index = get_mmio_addr_index(nodeid, link); + u32 index = 0; reg = 0x110 + (index << 24) + (6 << 20); // index could be 0, 63
} @@ -345,55 +302,6 @@ mmconf_resource(dev, MMIO_CONF_BASE); }
-static void set_resource(struct device *dev, struct resource *resource, - u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, - rend >> 8); - } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24), - rbase >> 8, rend >> 8, 1); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - #if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -433,8 +341,6 @@ static void nb_set_resources(struct device *dev) { unsigned int nodeid; - struct bus *bus; - struct resource *res;
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
@@ -443,64 +349,13 @@
create_vga_resource(dev, nodeid);
- /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } + pci_dev_set_resources(dev); }
/* Domain/Root Complex related code */
static void domain_read_resources(struct device *dev) { - unsigned int reg; - - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xc0; reg += 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = - new_resource(reg_dev, - IOINDEX(0x1000 + reg, - reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - -static void domain_set_resources(struct device *dev) -{ printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
@@ -513,6 +368,8 @@ u32 reset_memhole = 1; #endif
+ pci_domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); @@ -597,13 +454,6 @@ printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } - printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); }
static const char *domain_acpi_name(const struct device *dev) @@ -780,13 +630,13 @@ }
static struct device_operations northbridge_operations = { - .read_resources = nb_read_resources, - .set_resources = nb_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .read_resources = nb_read_resources, + .set_resources = nb_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, - .init = northbridge_init, - .enable = 0,.ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -804,9 +654,9 @@
static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .scan_bus = pci_domain_scan_bus, - .acpi_name = domain_acpi_name, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, };
static struct device_operations cpu_bus_ops = {
-
Michał Żygowski (Code Review)