Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52935 )
Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ......................................................................
nb/amd/agesa/family14/northbridge.c: Report missing resources
Not all resources were being reported, add them.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 49 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/1
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f58fc09..8ea4a96 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -239,19 +239,6 @@ } }
-static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) -{ - struct resource *min; - unsigned long mask_match = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - min = 0; - search_bus_resources(bus, mask_match, mask_match, tolm_test, - &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info { @@ -280,6 +267,36 @@ } #endif
+static void add_fixed_resources(struct device *dev, int index) +{ + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM + * 0xe0000 - 0xfffff: SeaBIOS, if used + */ + mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + + if (fx_devs == 0) + get_fx_devs(); + + /* + * Check if CC6 is enabled (bits [11:0] C6Base). Ff CC6 is not enabled, the base + * must be zero according to BKDG. + */ + if (pci_read_config32(__f4_dev[0], 0x12C) & 0xfff) { + resource_t c6basek; + c6basek = pci_read_config32(__f4_dev[0], 0x12C) & 0xfff; // [35:24] at [11:0] + /* + * Shift left by 24 bits for physical address and the convert to KiB by + * shifting 10 bits left. The C6Base is shifted 14 bits left thus no overflow. + */ + c6basek = c6basek << (24 - 10); + mmio_resource(dev, index++, c6basek, 16*1024); + } +} + static void nb_read_resources(struct device *dev) { u32 nodeid; @@ -300,6 +317,8 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + add_fixed_resources(dev, 0); }
#if CONFIG(CONSOLE_VGA_MULTI) @@ -360,9 +379,8 @@ printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
unsigned long mmio_basek; - u32 pci_tolm; + resource_t basek, limitk, sizek; // 4 1T int idx; - struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; @@ -370,21 +388,11 @@
pci_domain_read_resources(dev);
- pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } + /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ + mmio_basek = bsp_topmem() >> 10;
- // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) - 1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64 * 1024) - 1); + if (fx_devs == 0) + get_fx_devs();
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -403,7 +411,6 @@ #endif
idx = 0x10; - resource_t basek, limitk, sizek; // 4 1T
if (get_dram_base_limit(0, &basek, &limitk)) { sizek = limitk - basek; @@ -411,18 +418,16 @@ printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", basek, limitk, sizek);
- /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < 640) && (sizek > 768)) { - printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n"); - ram_resource(dev, (idx | 0), basek, 640 - basek); + /* see if we need a hole from 0xa0000 to 0xfffff */ + if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { + ram_resource(dev, idx, basek, (0xa0000 >> 10) - basek); idx += 0x10; - basek = 768; - sizek = limitk - 768; + basek = 0x100000 >> 10; + sizek = limitk - basek; }
- printk(BIOS_DEBUG, - "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + mmio_basek, basek, limitk);
/* split the region to accommodate pci memory space */ if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { @@ -440,16 +445,16 @@ if ((basek + sizek) <= 4 * 1024 * 1024) { sizek = 0; } else { + uint64_t topmem2 = bsp_topmem2(); basek = 4 * 1024 * 1024; - sizek -= (4 * 1024 * 1024 - mmio_basek); + sizek = topmem2 / 1024 - basek; } }
- ram_resource(dev, (idx | 0), basek, sizek); + ram_resource(dev, idx, basek, sizek); idx += 0x10; - printk(BIOS_DEBUG, - "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, - mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, + mmio_basek, basek, limitk); } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);