coreboot-gerrit May 2021

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Change in coreboot[master]: inteltool: add initial suppot for Sapphire Rapids Scalable Processor
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52863 ) Change subject: inteltool: add initial suppot for Sapphire Rapids Scalable Processor ...................................................................... Patch Set 1: (2 comments) File util/inteltool/inteltool.h: https://review.coreboot.org/c/coreboot/+/52863/comment/b0cf3494_e3f8054c PS1, Line 302: One tab too many? File util/inteltool/inteltool.c: https://review.coreboot.org/c/coreboot/+/52863/comment/7d011d36_718736f9 PS1, Line 146: Sacalable typo: S*calable -- To view, visit https://review.coreboot.org/c/coreboot/+/52863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf492d6e7993b9d55d6cd865e721c81876cee9a4 Gerrit-Change-Number: 52863 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 May 2021 12:05:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: inteltool: add initial support for Emmits Burg PCH
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52864 ) Change subject: inteltool: add initial support for Emmits Burg PCH ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4027bf51b3a189e64211e77621b3dd6c80b00d Gerrit-Change-Number: 52864 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 12:04:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: inteltool: add initial suppot for Sapphire Rapids Scalable Processor
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52863 ) Change subject: inteltool: add initial suppot for Sapphire Rapids Scalable Processor ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf492d6e7993b9d55d6cd865e721c81876cee9a4 Gerrit-Change-Number: 52863 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 12:04:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Remove bogus SMRAM locking
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51532 ) Change subject: soc/intel/xeon_sp: Remove bogus SMRAM locking ...................................................................... soc/intel/xeon_sp: Remove bogus SMRAM locking From tests this does not lock down SMRAM and it's also not possible to read back what is written, be it via PCI mmconfig or io ops. The FSP integration can be assumed to be bogus on this point. Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51532 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3eaf46f..9164b7c 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -182,14 +182,6 @@ /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - /* - * LOCK SMRAM - * According to the CedarIsland FSP Integration Guide this needs to - * be done with legacy 0xCF8/0xCFC IO ops. - */ - uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); - pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); - mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); set_imc_locks(); -- To view, visit https://review.coreboot.org/c/coreboot/+/51532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212 Gerrit-Change-Number: 51532 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52933 to look at the new patch set (#3). Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... lib/romstage_handoff.c: Initialize using a cbmem hook This reduces platform boilerplate code. Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/romstage_handoff.h M src/lib/romstage_handoff.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage.c 15 files changed, 7 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 2: Code-Review-1 (4 comments) Patchset: PS2: It looks functionally different on everything but fam14 File src/northbridge/amd/agesa/family15tn/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/be3e783e_0b98062f PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] This is gone? File src/northbridge/amd/agesa/family16kb/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/385489d9_df371e7b PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] This is gone? File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/01abc7d9_d3ad9aae PS2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] this is gone? -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 11:58:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Angel Pons (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Arthur Heymans, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52933 ) Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52933/comment/199934a7_61be6326 PS2, Line 9: boilplate boil*er*plate -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 11:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/*: Use acpi_is_wake_s3
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52932 ) Change subject: nb/intel/*: Use acpi_is_wake_s3 ...................................................................... Abandoned Not worth changing -- To view, visit https://review.coreboot.org/c/coreboot/+/52932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If71286bde340933e9e102daecb56ae34908fd5f5 Gerrit-Change-Number: 52932 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: sb/intel/common/pmclib: Use pmbase functions
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52939 ) Change subject: sb/intel/common/pmclib: Use pmbase functions ...................................................................... sb/intel/common/pmclib: Use pmbase functions Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/pmclib.c 1 file changed, 11 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/52939/1 diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 5bc0ef1..34a449b 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <stdint.h> #include <acpi/acpi.h> #include <console/console.h> @@ -8,31 +9,24 @@ #include "pmbase.h" #include "pmutil.h" +static void clear_power_state(void) +{ + uint32_t pm1_cnt = read_pmbase32(PM1_CNT); + write_pmbase32(PM1_CNT, pm1_cnt & ~SLP_TYP); +} + int southbridge_detect_s3_resume(void) { - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = read_pmbase16(PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = read_pmbase32(PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { - /* Clear SLP_TYPE. */ - write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); - is_s3 = 1; - } - } - if (is_s3) { + if (platform_is_resuming()) { + clear_power_state(); if (!acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); return 0; } printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); + return 1; } - return is_s3; + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Gerrit-Change-Number: 52939 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Angel Pons, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52933 to look at the new patch set (#2). Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... lib/romstage_handoff.c: Initialize using a cbmem hook This reduces platform boilplate code. Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/romstage_handoff.h M src/lib/romstage_handoff.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage.c 15 files changed, 7 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021