coreboot-gerrit May 2021

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Change in coreboot[master]: mb/amd/majolica: Enable S0i3 by default
by Marshall Dawson (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Paul Menzel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52857 ) Change subject: mb/amd/majolica: Enable S0i3 by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Gerrit-Change-Number: 52857 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 14:27:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN
by Subrata Banik (Code Review) 05 May '21

05 May '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52947 ) Change subject: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN ...................................................................... include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN Rename and updated POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba --- M src/include/console/post_codes.h M src/lib/hardwaremain.c 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52947/1 diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9682e4d..29d2a79 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -112,6 +112,14 @@ #define POST_PRE_HARDWAREMAIN 0x6e /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_HARDWAREMAIN 0x6f + +/** * \brief Before Device Probe * * Boot State Machine: bs_pre_device() @@ -196,14 +204,6 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 895a942..cd4a57e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -442,7 +442,7 @@ cbmem_initialize(); timestamp_add_now(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); + post_code(POST_ENTRY_HARDWAREMAIN); /* Handoff sleep type from romstage. */ acpi_is_wakeup_s3(); -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52895 to look at the new patch set (#4). Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... include/console: Fix duplicate entry of postcode 0x79 Changed POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/c_start.S M src/include/console/post_codes.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52895/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Update AMDFW config file
by chris wang (Code Review) 05 May '21

05 May '21

Attention is currently required from: Martin Roth, Marshall Dawson. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52900 ) Change subject: mb/google/mancomb: Update AMDFW config file ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg: https://review.coreboot.org/c/coreboot/+/52900/comment/a249307a_2d3138d6 PS1, Line 37: PSP_PMUI_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin : PSP_PMUD_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin > It looks like you transposed the I and D in col. 8, comparing to soc//cezanne. […] It should like below. PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/52900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Gerrit-Change-Number: 52900 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:21:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{picasso/common}: Move populate_pirq_data to common
by Felix Held (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52912 ) Change subject: soc/amd/{picasso/common}: Move populate_pirq_data to common ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52912/comment/9c2cfb2d_a8789c23 PS1, Line 7: Move populate_pirq_data to common "Move populate_pirq_data prototype to common" would be more specific -- To view, visit https://review.coreboot.org/c/coreboot/+/52912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Gerrit-Change-Number: 52912 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Add Kconfig/Makefile support for common/fsp/*
by Felix Held (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52910 ) Change subject: soc/amd/common: Add Kconfig/Makefile support for common/fsp/* ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: good idea -- To view, visit https://review.coreboot.org/c/coreboot/+/52910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Gerrit-Change-Number: 52910 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52895/comment/02085df6_b674da3d PS3, Line 13: to make the ramstage postcodes appear in an incremental order. > make sense, will wait for Nico to share his thought on this and then i will split this CL? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:18:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
by Felix Held (Code Review) 05 May '21

05 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Matt Papageorge, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52869 ) Change subject: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID ...................................................................... Patch Set 2: Code-Review+2 (2 comments) File src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h: https://review.coreboot.org/c/coreboot/+/52869/comment/2ab613ce_c08784e6 PS1, Line 38: static inline const struct pcie_routing_info *get_pcie_routing_info(unsigned int devfn) > i wouldn't put the two functions here in a header in the vendorcode directory, but move them to the […] Done https://review.coreboot.org/c/coreboot/+/52869/comment/b03f6633_b149b69f PS1, Line 43: fsp_find_extension_hob_by_guid > since this function call is rather expensive in terms of time, i wouldn't do the call for every irq […] moved to CB:52911 -- To view, visit https://review.coreboot.org/c/coreboot/+/52869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Gerrit-Change-Number: 52869 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:18:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Felix Held (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52911 ) Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/fsp/pci/pci_routing_info.c: https://review.coreboot.org/c/coreboot/+/52911/comment/55eb827b_7e2a342f PS1, Line 29: routing_table > Can this be a static variable, so that we can lookup the HOB once and then re-use it for subsequent […] i'd also strongly recommend that, since the search for the hob is rather expensive in terms of time -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 3: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/608c03f7_4e4bab05 PS3, Line 190: POST_BS_WRITE_TABLES > make sense @Angel, as we are planning to move POST_PRE_HARDWAREMAIN and POST_ENTRY_RAMSTAGE between 0x6e and 0x6f, do you think we can keep POST_BS_WRITE_TABLES as 0x79 to maintain the order. Otherwise i might need to change postcode after this as well. btw, POST_BS_PAYLOAD_LOAD and POST_BS_PAYLOAD_BOOT also not in use. -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 May 2021 14:00:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021