coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: sb/intel/common: Implement acpi_is_wakeup_s3()
by Patrick Rudolph (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52929 ) Change subject: sb/intel/common: Implement acpi_is_wakeup_s3() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Gerrit-Change-Number: 52929 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 05 May 2021 15:43:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
by Raul Rangel (Code Review) 05 May '21

05 May '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52801 ) Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration ...................................................................... mb/google/guybrush: Fix S0i3/S3 GPIO configuration Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=Wake system from S0i3 with EC and see GPE 3 increment. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 528ace1..336fd62 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -27,7 +27,7 @@ /* EN_PWR_WWAN_X */ PAD_GPO(GPIO_8, HIGH), /* SOC_TCHPAD_INT_ODL */ - PAD_INT(GPIO_9, PULL_NONE, EDGE_HIGH, STATUS_DELIVERY), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH), /* S0A3 */ PAD_NF(GPIO_10, S0A3, PULL_NONE), /* SOC_FP_RST_L */ @@ -38,7 +38,7 @@ /* USB_OC0_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), /* SOC_SAR_INT_L */ - PAD_INT(GPIO_17, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, LOW), /* I2C3_SCL */ @@ -46,9 +46,9 @@ /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* SOC_FP_INT_L */ - PAD_INT(GPIO_21, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + PAD_SCI(GPIO_21, PULL_NONE, EDGE_LOW), /* EC_SOC_WAKE_ODL */ - PAD_WAKE(GPIO_22, PULL_NONE, EDGE_LOW, S0i3), + PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* WWAN_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Gerrit-Change-Number: 52801 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52801 ) Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52801/comment/f272da22_50ab91e7 PS3, Line 40: SOC_SAR_INT_L > Aah. I don't really see that as a wake requirement in go/cros-partner-docs though. […] I'm not sure... I'll post on the bug. Thanks for raising this. -- To view, visit https://review.coreboot.org/c/coreboot/+/52801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c Gerrit-Change-Number: 52801 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 15:31:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 15:16:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP-T position
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP-T position ...................................................................... drivers/intel/fsp2_0: Fix the FSP-T position The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 3 files changed, 8 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 63394dd4..3b03b6d 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -74,6 +74,12 @@ depends on FSP_CAR default "fspt.bin" +config FSP_T_LOCATION + hex + default 0xfffe0000 + help + The location for FSP-T. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 92f6711..3bbc722 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -48,6 +48,7 @@ $(FSP_T_CBFS)-type := fsp ifeq ($(CONFIG_FSP_T_XIP),y) $(FSP_T_CBFS)-options := --xip $(TXTIBB) +$(FSP_T_CBFS)-position = $(CONFIG_FSP_T_LOCATION) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_M_CBFS) diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index a2e85b9..173ebf7 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -21,16 +21,7 @@ cache_as_ram: post_code(0x21) - /* find fsp in cbfs */ - lea fsp_name, %esi - mov $1f, %esp - jmp walkcbfs_asm -1: - cmp $0, %eax - jz .halt_forever - mov CBFS_FILE_OFFSET(%eax), %ebx - bswap %ebx - add %eax, %ebx + movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx /* -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP-T position
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Michał Żygowski, Paul Menzel, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP-T position ...................................................................... Patch Set 4: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/52850/comment/b61688dd_acc98f1a PS2, Line 81: The location for FSP-T. > > This value should be also set per SoC. It may differ across FSP releases. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 15:14:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/amd/majolica: Enable S0i3 by default
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Paul Menzel, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52857 ) Change subject: mb/amd/majolica: Enable S0i3 by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Gerrit-Change-Number: 52857 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 14:47:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52879 ) Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52879/comment/50a9fef7_5b688b6b PS4, Line 16: Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> > double signed off Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 May 2021 14:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Julius Werner, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52879 to look at the new patch set (#5). Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc M src/arch/x86/walkcbfs.S 2 files changed, 6 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52879/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Martin Roth, Marshall Dawson, Julian Schroeder, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52909 ) Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp ...................................................................... Patch Set 1: (1 comment) File src/vendorcode/amd/fsp/cezanne/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/52909/comment/d171e66b_f5e26b33 PS1, Line 110: sh_oem What does the sh_oem stand for? -- To view, visit https://review.coreboot.org/c/coreboot/+/52909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d Gerrit-Change-Number: 52909 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 14:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021