coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: add check for maximum table size
by Felix Held (Code Review) 05 May '21

05 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52897 ) Change subject: soc/amd/common/fsp/fsp-acpi: add check for maximum table size ...................................................................... soc/amd/common/fsp/fsp-acpi: add check for maximum table size If the ACPI table size in the HOB data header is larger than the maximum HOB payload, don't add the table at all and print an error instead, since in this case the memcpy would read past the end of the HOB data structure. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52897 Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/fsp/fsp-acpi.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/fsp/fsp-acpi.c b/src/soc/amd/common/fsp/fsp-acpi.c index b530688..f92d571 100644 --- a/src/soc/amd/common/fsp/fsp-acpi.c +++ b/src/soc/amd/common/fsp/fsp-acpi.c @@ -28,6 +28,12 @@ return current; } + if (data->table_size_in_bytes > sizeof(data->hob_payload)) { + printk(BIOS_ERR, "AGESA %s ACPI table size larger than maximum HOB payload " + "size.\n", name); + return current; + } + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); memcpy(table, data->hob_payload, data->table_size_in_bytes); -- To view, visit https://review.coreboot.org/c/coreboot/+/52897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50 Gerrit-Change-Number: 52897 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality
by Felix Held (Code Review) 05 May '21

05 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52896 ) Change subject: soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality ...................................................................... soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality This function will be reused in Cezanne, so move it from the Picasso directory to the common FSP integration code. TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp-acpi.c M src/soc/amd/picasso/agesa_acpi.c 4 files changed, 46 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 215d668..eec5a3f 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -56,4 +56,7 @@ unsigned long acpi_fill_madt_irqoverride(unsigned long current); void acpi_fill_root_complex_tom(const struct device *device); +uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current); + #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index 5523876..3ba6ea5 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -1,4 +1,5 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += fsp_reset.c ramstage-y += fsp_reset.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c endif # CONFIG_PLATFORM_USES_FSP2_0 diff --git a/src/soc/amd/common/fsp/fsp-acpi.c b/src/soc/amd/common/fsp/fsp-acpi.c new file mode 100644 index 0000000..b530688 --- /dev/null +++ b/src/soc/amd/common/fsp/fsp-acpi.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <console/console.h> +#include <fsp/util.h> +#include <string.h> +#include <types.h> + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; /* maximum payload size */ +} __packed; + +uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index b5982c8..5122be5 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -6,12 +6,12 @@ #include <console/console.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> -#include <fsp/util.h> #include <FspGuids.h> #include <soc/acpi.h> #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <amdblocks/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> @@ -20,38 +20,6 @@ #include <stdlib.h> #include <arch/mmio.h> -struct amd_fsp_acpi_hob_info { - uint32_t table_size_in_bytes; - uint8_t total_hobs_for_table; - uint8_t sequence_number; - uint16_t reserved; - uint16_t hob_payload[0xffc8]; -} __packed; - -static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, - uintptr_t current) -{ - const struct amd_fsp_acpi_hob_info *data; - void *table = (void *)current; - size_t hob_size; - - data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); - if (!data) { - printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); - return current; - } - - printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); - - memcpy(table, data->hob_payload, data->table_size_in_bytes); - - current += data->table_size_in_bytes; - acpi_add_table(rsdp, table); - current = acpi_align_current(current); - - return current; -} - unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -1033,7 +1001,7 @@ current += crat->header.length; acpi_add_table(rsdp, crat); - current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ current = ALIGN(current, 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/52896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Gerrit-Change-Number: 52896 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Nick Vaccaro (Code Review) 05 May '21

05 May '21

Attention is currently required from: Kevin Chang, Caveh Jalali. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... Patch Set 13: (2 comments) File src/mainboard/google/volteer/variants/volteer2/gpio.c: https://review.coreboot.org/c/coreboot/+/47501/comment/8eff424e_eee66f3c PS13, Line 3: variant nit - alphabetical order File src/mainboard/google/volteer/variants/volteer2/variant.c: https://review.coreboot.org/c/coreboot/+/47501/comment/86c202ad_c2378a56 PS13, Line 19: _up > _dn If you can update this, I'll +2 and we can merge this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 13 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 18:02:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE
by Nick Vaccaro (Code Review) 05 May '21

05 May '21

Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52742 ) Change subject: cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9fdae7cdf812d92a4d3b61368de884f4e55aa3a Gerrit-Change-Number: 52742 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/volteer/var/elemi: Add spd for K4AAG165WB-BCWE
by Nick Vaccaro (Code Review) 05 May '21

05 May '21

Attention is currently required from: Chen Wisley. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52880 ) Change subject: mb/google/volteer/var/elemi: Add spd for K4AAG165WB-BCWE ...................................................................... Patch Set 1: Code-Review+2 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/52880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a Gerrit-Change-Number: 52880 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Comment-Date: Wed, 05 May 2021 17:34:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update xhci device tree
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: David Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede/var/metaknight: Update xhci device tree ...................................................................... Patch Set 2: (3 comments) Patchset: PS2: So far the approach is fine. Please configure the settings as provided in the devicetree File src/mainboard/google/dedede/variants/metaknight/variant.c: https://review.coreboot.org/c/coreboot/+/52887/comment/02d51ac3_5d4da5a6 PS2, Line 36: /* Set 1A HDMI configuration */ Leave USB Port A as a default configuration in the devicetree. Then you dont need to handle this case. https://review.coreboot.org/c/coreboot/+/52887/comment/73602689_299cfdbe PS2, Line 38: /* Set LTE HDMI configuration */ Configure the settings as in the devicetree. One element in the drivers_usb_acpi_config structure (desc) is a const variable. You may need to leave it generic enough in the device tree and not touch it. memset the config->group to 0 Configure the rest of the elements in config as in the devicetree for LTE. -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 May 2021 17:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Enable S0i3 by default
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Paul Menzel, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52857 ) Change subject: mb/amd/majolica: Enable S0i3 by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Gerrit-Change-Number: 52857 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 16:51:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Patrick Rudolph (Code Review) 05 May '21

05 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Arthur Heymans, Kyösti Mälkki, Andrey Petrov. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52933 ) Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 15:48:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common/pmclib: Use pmbase functions
by Patrick Rudolph (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52939 ) Change subject: sb/intel/common/pmclib: Use pmbase functions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Gerrit-Change-Number: 52939 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 05 May 2021 15:46:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common: Fix platform_is_resuming()
by Patrick Rudolph (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52930 ) Change subject: sb/intel/common: Fix platform_is_resuming() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Gerrit-Change-Number: 52930 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 05 May 2021 15:44:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021