coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Arthur Heymans, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 2: (3 comments) File src/northbridge/amd/agesa/family15tn/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/1f7bb919_88db8007 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > Yes it is gone, we would need to support at least ~256GB of DRAM memory to have any other value than […] resource_t is uint64_t so for completeness I could add the higher DRAM limit bits. File src/northbridge/amd/agesa/family16kb/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/37c66458_5cecfeed PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > As above. Also no point in checking those since Kabini CONFIG_CPU_ADDR_BITS is 40, 40 bits are covered by 0x44 register File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/713d2ab0_0a14bf08 PS2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > As above Also for some reason, the 0x144 register is reserved on 00730F01, even in NDA BKDG. Probably removed due to max 40 physical address bits. -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 12:53:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [TEST]soc/intel/braswell: Use cbfs mcache
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52943 ) Change subject: [TEST]soc/intel/braswell: Use cbfs mcache ...................................................................... [TEST]soc/intel/braswell: Use cbfs mcache Change-Id: I2cfdd40313147034be691492d2eb9b17293200b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/52943/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 0e1b6db..2b6d672 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -43,7 +43,6 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - select NO_CBFS_MCACHE config DCACHE_BSP_STACK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/52943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cfdd40313147034be691492d2eb9b17293200b0 Gerrit-Change-Number: 52943 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52942 ) Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ...................................................................... cpu/intel/socket_p: Increase DCACHE_RAM_SIZE All CPUs supported by this socket should have plenty of cache. This allows the use of cbfs mcache on all platforms. Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_p/Kconfig M src/mainboard/lenovo/t400/Kconfig 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52942/1 diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index a7c8ab1..7e9cca3 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -13,7 +13,7 @@ config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000 config DCACHE_BSP_STACK_SIZE hex diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 809ea45..5b3ecf1 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -26,7 +26,6 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT - select NO_CBFS_MCACHE config VBOOT select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/52942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Gerrit-Change-Number: 52942 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: nb/intel/pineview: Use cbfs mcache
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52941 ) Change subject: nb/intel/pineview: Use cbfs mcache ...................................................................... nb/intel/pineview: Use cbfs mcache There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache. Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/northbridge/intel/pineview/Kconfig 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/52941/1 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 5105f09..31926b8 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -18,7 +18,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 config DCACHE_BSP_STACK_SIZE hex diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 0ff437a..fc9c8f1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -14,7 +14,6 @@ select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP - select NO_CBFS_MCACHE config VGA_BIOS_ID string -- To view, visit https://review.coreboot.org/c/coreboot/+/52941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Gerrit-Change-Number: 52941 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52879 ) Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52879/comment/24328d7e_ba305e20 PS2, Line 7: instead > nit: instead *of* Done https://review.coreboot.org/c/coreboot/+/52879/comment/7810f601_b2ae73fc PS2, Line 13: the cbfs master header removed. > nit: since this line is a continuation of the previous line, I'd indent it with two spaces to accoun […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 12:26:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Julius Werner, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Julius Werner, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52879 to look at the new patch set (#4). Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc M src/arch/x86/walkcbfs.S 2 files changed, 6 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52879/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86: Always include walkcbfs.S
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52940 ) Change subject: arch/x86: Always include walkcbfs.S ...................................................................... arch/x86: Always include walkcbfs.S Let the linker decide if this code is needed. Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc M src/cpu/qemu-x86/Makefile.inc 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/52940/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7dea2ce..0cb6e92 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -91,7 +91,7 @@ $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif -bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += walkcbfs.S +bootblock-y += walkcbfs.S endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 3f27e8b..fb560d6 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c -bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S romstage-y += ../intel/car/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/52940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Gerrit-Change-Number: 52940 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead "cbfs master header"
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Julius Werner, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Julius Werner, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52879 to look at the new patch set (#3). Change subject: arch/x86/walkcbfs.S: Use FMAP instead "cbfs master header" ...................................................................... arch/x86/walkcbfs.S: Use FMAP instead "cbfs master header" Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc M src/arch/x86/walkcbfs.S 2 files changed, 6 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52879/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 05 May '21

05 May '21

Attention is currently required from: Nico Huber, Arthur Heymans, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 2: (4 comments) Patchset: PS2: > It looks functionally different on everything but fam14 I don't exactly understand what is different? Could you elaborate? File src/northbridge/amd/agesa/family15tn/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/c8bd81b8_94a87066 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > This is gone? Yes it is gone, we would need to support at least ~256GB of DRAM memory to have any other value than 0 in this register. Although CONFIG_CPU_ADDR_BITS is 48 (for virtual address space) this register describes only real DRAM in the system. I made a simplification based on reasonable conclusion that such an old system's mobile memory controller cannot support more than 16GB or 32GB of DRAM. File src/northbridge/amd/agesa/family16kb/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/025c3a63_2fb67325 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > This is gone? As above. File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/22392ad1_36b8dc58 PS2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] > this is gone? As above -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 05 May 2021 12:22:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/magolor: Select elan hidi2c address based on SSF...
by David Wu (Code Review) 05 May '21

05 May '21

Attention is currently required from: David Wu, Henry Sun. Hello build bot (Jenkins), Henry Sun, Marco Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52851 to look at the new patch set (#3). Change subject: mb/google/dedede/var/magolor: Select elan hidi2c address based on SSFC value ...................................................................... mb/google/dedede/var/magolor: Select elan hidi2c address based on SSFC value Select elan hidi2c address 0x10 for magister, based on the value set in the SSFC_CONFIG. BUG=b:186609348 TEST=build and boot to OS. Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/52851/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021