Attention is currently required from: Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52942 )
Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ......................................................................
cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
All CPUs supported by this socket should have plenty of cache. This allows the use of cbfs mcache on all platforms.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_p/Kconfig M src/mainboard/lenovo/t400/Kconfig 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52942/1
diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index a7c8ab1..7e9cca3 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -13,7 +13,7 @@
config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000
config DCACHE_BSP_STACK_SIZE hex diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 809ea45..5b3ecf1 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -26,7 +26,6 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT - select NO_CBFS_MCACHE
config VBOOT select VBOOT_VBNV_CMOS