Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52941 )
Change subject: nb/intel/pineview: Use cbfs mcache ......................................................................
nb/intel/pineview: Use cbfs mcache
There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache.
Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/northbridge/intel/pineview/Kconfig 2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/52941/1
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 5105f09..31926b8 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -18,7 +18,7 @@
config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000
config DCACHE_BSP_STACK_SIZE hex diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 0ff437a..fc9c8f1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -14,7 +14,6 @@ select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP - select NO_CBFS_MCACHE
config VGA_BIOS_ID string